Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 LP2992 Micropower 250-mA Low-Noise Ultra-Low-Dropout Regulator in SOT-23 and WSON Packages Designed for Use With Very Low-ESR Output Capacitors 1 Features 3 Description * * * * * * * * * * * * * * The LP2992 is a 250-mA, fixed-output voltage regulator designed to provide ultra-low dropout and low noise in battery-powered applications. 1 * * Input Voltage Range: 2.2 V to 16 V Output Voltage Range: 1.5 V to 5 V Wide Supply Voltage Range (16-V Maximum) Output Voltage Accuracy 1% (A Grade) Ultra-Low-Dropout Voltage Specified 250-mA Output Current Stable With Low-ESR Output Capacitor < 1-A Quiescent Current When Shut Down Low Ground Pin Current at All Loads High Peak Current Capability Low ZOUT: 0.3- Typical (10 Hz to 1 MHz) Overtemperature and Overcurrent Protection -40C to +125C Junction Temperature Range Smallest Possible Size (SOT-23, WSON Package) Requires Minimum External Components Custom Voltages Available Using an optimized vertically integrated PNP (VIP) process, the LP2992 delivers unequaled performance in all specifications critical to battery-powered designs: * Dropout voltage: Typically 450 mV at 250-mA load, and 5 mV at 1-mA load. * Ground pin current: Typically 1500 A at 250-mA load, and 75 A at 1-mA load. * Enhanced stability: The LP2992 is stable with output capacitor equivalent series resistance (ESR) as low as 5 m, which allows the use of ceramic capacitors on the output. * Sleep mode: Less than 1-A quiescent current when ON/OFF pin is pulled low. * Smallest possible size: SOT-23 and WSON packages use absolute minimum board space. * Precision output: 1% tolerance output voltages available (A grade). * Low noise: By adding a 10-nF bypass capacitor, output noise can be reduced to 30 V (typical). * Multiple voltage options, from 1.5 V to 5 V, are available as standard products. Consult factory for custom voltages. 2 Applications * * * * Cellular Phones Palmtop/Laptop Computers Personal Digital Assistants (PDA) Camcorders, Personal Stereos, Cameras Device Information(1) PART NUMBER LP2992 PACKAGE BODY SIZE (NOM) WSON (6) 3.29 mm x 2.92 mm SOT-23 (5) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VIN IN VOUT OUT CIN LP2992 COUT GND VON/OFF ON/OFF ON OFF BYPASS CBYPASS Copyright (c) 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 13 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 13 13 13 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application ................................................. 15 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Examples................................................... 21 10.3 WSON Mounting ................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (November 2015) to Revision J Page * Deleted specific values from capacitors in Simplified Schematic drawing ............................................................................ 1 * Added Receiving Notification of Documentation Updates ................................................................................................... 22 Changes from Revision H (January 2015) to Revision I Page * Added top navigator icon for TI Design ................................................................................................................................. 1 * Changed "174.2C/W" to "169.7C/W" in footnote 3 to Abs Max table. ................................................................................ 4 * Changed ESD Ratings table to differentiate different values for different pins/packages. .................................................... 4 * Added new footnotes 2 and 3 to Thermal Information table; update thermal values for DBV (SOT-23) package. ............... 5 * Added Power Dissipation and Estimating Junction Temperature subsections ................................................................... 18 * Added additional related document links ............................................................................................................................. 22 Changes from Revision G (March 2013) to Revision H * Added Device Information and ESD Ratings tables, Pin Configuration and Functions, Feature Description , Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout , Device and Documentation Support , and Mechanical, Packaging, and Orderable Information sections; update Thermal Values and pin names ........................................................................................................................................................................ 1 Changes from Revision F (March 2013) to Revision G * 2 Page Page Changed Changed layout of National Semiconductor data sheet to TI format ..................................................................... 1 Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View NGD Package 6-Pin WSON Top View Pin Functions PIN NAME I/O DESCRIPTION DBV NAME NGD BYPASS 4 BYPASS 1 I Bypass capacitor for low-noise operation. GND 2 GND 2 - Ground. IN 1 IN 4 I Unregulated input voltage. - - N/C 5 - No internal connection. Connect to GND or leave open. ON/OFF 3 ON/OFF 3 I A low voltage on this pin disables the device, and the regulator enters a sleep mode. A high voltage on this pin enables the device. OUT 5 OUT 6 O Regulated output voltage. This pin requires an output capacitor to maintain stability. See the Detailed Design Procedure for output capacitor details. -- -- DAP Exposed thermal pad -- The exposed die attach pad on the bottom of the package must be connected to a copper thermal pad on the PCB at ground potential. Connect to ground potential or leave floating. Do not connect to any potential other than the same ground potential seen at device pin 2. Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 3 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN Lead temperature (soldering, 5 seconds) Power dissipation (3) MAX UNIT 260 C Internally Limited Input supply voltage (survival) -0.3 16 V Shutdown input voltage (survival) -0.3 16 V -0.3 9 V Output voltage (survival) (4) IOUT (survival) Short-circuit protected Input-output voltage (survival) (5) -0.3 16 V Storage temperature, Tstg -65 150 C (1) (2) (3) (4) (5) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military- or Aerospace-specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, RJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: P(MAX) = (TJ(MAX) - TA) / RJA Where the value of RJA for the SOT-23 package is 169.7C/W in a typical PC board mounting and the WSON package is 72.3C/W. Exceeding the maximum allowable dissipation causes excessive die temperature, and the regulator goes into thermal shutdown. If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2992 output must be diode-clamped to ground. The output PNP structure contains a diode between the IN to OUT pins that is normally reverse-biased. Reversing the polarity from VIN to VOUT turns on this diode. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Pins 3 and 4 (SOT) Pins 1 and 3 (WSON) 1000 All pins except 3 and 4 (SOT) All pins except 1 and 3 (WSON) 2000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN Input supply voltage VON/OFF ON/OFF input voltage IOUT Output current TJ Operating junction temperature (1) 4 MIN MAX 2.2 (1) 16 0 -40 UNIT V VIN V 250 mA 125 C Recommended minimum VIN is the greater of 2.2 V or VOUT + rated dropout voltage (maximum) for operating load current. Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 6.4 Thermal Information LP2992 THERMAL METRIC (1) DBV (SOT-23) NGD (WSON) (2) 5 PINS 6 PINS UNIT RJA (3) Junction-to-ambient thermal resistance 169.7 72.3 C/W RJC(top) Junction-to-case (top) thermal resistance, High K 122.6 81.6 C/W RJB Junction-to-board thermal resistance 29.9 39.5 C/W JT Junction-to-top characterization parameter 16.7 2.0 C/W JB Junction-to-board characterization parameter 29.4 39.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance n/a 11.6 C/W (1) (2) (3) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics. The PCB for the NGD (WSON) package RJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5. Thermal resistance value RJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. 6.5 Electrical Characteristics Unless otherwise specified: VIN = VOUT(NOM) + 1 V, IL = 1 mA, CIN = 1 F, COUT = 4.7 F, VON/OFF = 2 V. MIN (minimum) and MAX (maximum) limits apply over the recommended operating temperature range unless otherwise noted; typical limits apply for TA = TJ = 25C. PARAMETER TEST CONDITIONS TYP VOUT/VIN Output voltage tolerance Output voltage line regulation -1.5 1.5 -2.5 2.5 1 mA IL 50 mA -2.5 2.5 -3.5 3.5 %VNOM 1 mA IL 250 mA, TJ = 25C -3.5 3.5 -4 4 1 mA IL 250 mA -4.5 4.5 -5 5 VOUT(NOM) + 1 V VIN 16 V TJ = 25C 0.007 0.014 0.014 0.032 0.032 2.05 2.2 2.2 0.5 2.5 2.5 4 4 IL = 1 mA, TJ = 25C 5 IL = 1 mA IL = 50 mA, TJ = 25C 100 IL = 50 mA IL = 150 mA, TJ = 25C 260 IL = 150 mA IL = 250 mA, TJ = 25C 450 IL = 250 mA (2) UNIT 1 IL = 0 mA (1) MAX 1.5 Minimum input voltage required to maintain output regulation Dropout voltage (2) MIN -1 IL = 0 mA, TJ = 25C VIN - VOUT MAX -1.5 VOUT(NOM) + 1 V VIN 16 V VIN(min) MIN LP2992I-X.X (1) 1 mA IL 50 mA, TJ = 25C IL = 1 mA, TJ = 25C VOUT LP2992AI-X.X (1) 9 9 12 12 125 125 180 180 325 325 470 470 575 575 850 850 %/V V mV Limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). VIN must be the greater of 2.2 V or VOUT(NOM) + dropout voltage to maintain output regulation. Dropout voltage is defined as the input-tooutput differential at which the output voltage drops 2% below the value measured with a 1-V differential. Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 5 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VIN = VOUT(NOM) + 1 V, IL = 1 mA, CIN = 1 F, COUT = 4.7 F, VON/OFF = 2 V. MIN (minimum) and MAX (maximum) limits apply over the recommended operating temperature range unless otherwise noted; typical limits apply for TA = TJ = 25C. PARAMETER TEST CONDITIONS TYP IL = 0 mA, TJ = 25C LP2992AI-X.X (1) MIN 65 IL = 0 mA IL = 1 mA, TJ = 25C 75 IL = 1 mA IL = 50 mA, TJ = 25C IGND Ground pin current 350 IL = 50 mA IL = 150 mA, TJ = 25C 850 IL = 150 mA IL = 250 mA, TJ = 25C 1500 IL = 250 mA VON/OFF ON/OFF input voltage (3) ION/OFF ON/OFF input current en MAX LP2992I-X.X (1) MIN MAX 95 95 125 125 110 110 170 170 600 600 1000 1000 1500 1500 2500 2500 2300 2300 4000 4000 0.8 0.8 VON/OFF < 0.3 V, TJ = 25C 0.01 VON/OFF < 0.15 V 0.05 High = O/P ON 1.4 Low = O/P OFF 0.55 0.15 0.15 VON/OFF = 0 2 1.6 UNIT A 2 1.6 V 0.01 -2 -2 VON/OFF = 5 V 5 15 15 Output noise voltage (RMS) Bandwidth = 300 Hz to 50 kHz COUT = 10 F CBYPASS = 10 nF 30 V VOUT/VIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF COUT = 10 F 45 dB IO(SC) Short-circuit current RL = 0 (steady state) (4) 400 mA IO(PK) Peak output current VOUT VO(NOM) - 5% 350 mA (3) (4) 6 A The ON/OFF input must be properly driven to prevent possible mis-operation. For details, see Operation with ON/OFF Control. The LP2992 has thermal foldback current limiting which allows a high peak current when VOUT > 0.5 V, and then reduces the maximum output current as VOUT is forced to ground (see Typical Characteristics curves). Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 6.6 Typical Characteristics Unless otherwise specified: CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) + 1 V, TA = 25C, ON/OFF pin is tied to the IN pin. Figure 1. VOUT vs Temperature Figure 2. Short-Circuit Current Figure 3. Short-Circuit Current Figure 4. Short-Circuit Current vs Output Voltage Figure 5. Ripple Rejection Figure 6. Ripple Rejection Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 7 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified: CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) + 1 V, TA = 25C, ON/OFF pin is tied to the IN pin. 8 Figure 7. Ripple Rejection Figure 8. Ripple Rejection Figure 9. Ripple Rejection Figure 10. Ripple Rejection Figure 11. Ripple Rejection Figure 12. Ripple Rejection Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 Typical Characteristics (continued) Unless otherwise specified: CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) + 1 V, TA = 25C, ON/OFF pin is tied to the IN pin. Figure 13. Ripple Rejection Figure 14. Output Impedance vs Frequency Figure 15. Output Impedance vs Frequency Figure 16. Output Noise Density Figure 17. Output Noise Density Figure 18. GND Pin vs Load Current Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 9 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified: CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) + 1 V, TA = 25C, ON/OFF pin is tied to the IN pin. 10 Figure 19. Dropout Voltage vs Temperature Figure 20. Input Current vs Pin Figure 21. IGND vs Load and Temperature Figure 22. Instantaneous Short-Circuit Current Figure 23. Load Transient Response Figure 24. Load Transient Response Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 Typical Characteristics (continued) Unless otherwise specified: CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) + 1 V, TA = 25C, ON/OFF pin is tied to the IN pin. Figure 25. Load Transient Response Figure 26. Line Transient Response Figure 27. Line Transient Response Figure 28. Line Transient Response Figure 29. Line Transient Response Figure 30. Turnon Time Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 11 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified: CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) + 1 V, TA = 25C, ON/OFF pin is tied to the IN pin. Figure 32. Turnon Time Figure 31. Turnon Time Figure 33. Turnon Time 12 Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 7 Detailed Description 7.1 Overview The LP2992 family of fixed-output, ultralow-dropout, and low-noise regulators offer exceptional and cost-effective performance for battery-powered applications. Available in output voltages from 1.5 V to 5 V, the family has an output tolerance of 1% for the A version and is capable of delivering 250-mA continuous load current. Using an optimized vertically integrated PNP (VIP) process, the LP2992 delivers unequaled performance. The dropout voltage and the GND pin current with 250 mA of load current are typically 450 mV and 1500 A, respectively. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Sleep Mode When the ON/OFF pin is pulled low, the LP2992 enters a sleep mode, and less than 1-A quiescent current is consumed. This function is designed for the application which needs a sleep mode to effectively enhance battery life cycle. 7.3.2 Low Ground Current The LP2992 uses a vertical PNP process which allows for quiescent currents which are considerably lower than those associated with traditional lateral PNP regulators, typically 1500 A at 250-mA load and 75 A at 1-mA load. 7.3.3 Low Noise The LP2992 includes a low-noise reference ensuring minimal noise during operation because the internal reference is normally the dominant term in a noise analysis. Further noise reduction can be achieved by adding an external bypass capacitor between the BYPASS pin and the GND pin. For more detailed information on noise reduction using the BYPASS pin, see Noise Bypass Capacitor. 7.3.4 Enhanced Stability The LP2992 is designed specifically to work with ceramic output capacitors using circuitry that allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 5 m. For output capacitor requirements, see Output Capacitor. Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 13 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com Feature Description (continued) 7.3.5 Overcurrent Protection The internal current-limit circuit is used to protect the LDO against high-current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when the output impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output. The LP2992 is featured with the foldback current limit that allows a high peak current when VOUT > 0.5 V, and then reduces the maximum output current as VOUT is forced to ground. 7.3.6 Overtemperature Protection The LP2992 is designed with the thermal shutdown circuitry to turn off the output when excessive heat is dissipated in the LDO. The internal protection circuitry of the LP2992 is designed to protect against thermal overload conditions. Continuously running the device into thermal shutdown degrades its reliability. 7.4 Device Functional Modes 7.4.1 Operation with VOUT(TARGET) + 0.9 V VIN 16 V The LP2992 operates if the input voltage is equal to or exceeds VOUT(TARGET) + 0.9 V. At input voltages below the minimum VIN requirement, the device does not operate correctly and output voltage may not reach a target value. 7.4.2 Operation with ON/OFF Control If the voltage on the ON/OFF pin is less than 0.15 V, the device is disabled and, in this shutdown state, current does not exceed 2 A. Raising the voltage at the ON/OFF pin above 1.6 V initiates the start-up sequence of the device. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator output on at all times. To assure proper operation, the signal source used to drive the ON/OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds listed in the Electrical Characteristics section under VON/OFF. To prevent mis-operation, the turnon (and turnoff) voltage signals applied to the ON/OFF input must have a slew rate which is 40 mV/s. CAUTION The regulator output voltage can not be ensured if a slow-moving AC (or DC) signal is applied that is in the range between the specified turnon and turnoff voltages listed under the electrical specification VON/OFF (see Electrical Characteristics). 14 Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP2992 is a 250-mA, fixed-output voltage regulator designed to provide ultralow-dropout and low noise in battery powered applications. The device is stable with output capacitor equivalent series resistance (ESR) as low as 5 m which allows the use of ceramic capacitors on the output. At 250-mA loading, the dropout voltage of the LP2992 is 850 mV maximum over temperature; thus, 1000-mV headroom is sufficient for operation over input and output voltage accuracy. The efficiency of the LP2992 in this configuration is VOUT/VIN = 76.7%. To achieve the smallest form factor, the SOT-23 package is selected. Input and output capacitors are selected in accordance with Capacitor Characteristics. Ceramic capacitance of 1 F for the input and that of 4.7 F for the output are selected. With efficiency of 76.7% and a 250-mA load current, the internal power dissipation is 250 mW, which corresponds to 43.55C junction temperature rise for the SOT-23 package. To minimize noise, a bypass capacitor (CBYPASS) of 0.01 F is selected. 8.2 Typical Application *ON/OFF input must be actively terminated. Tie to the IN pin if this function is not to be used. **Minimum capacitance is shown to ensure stability (may be increased without limit). Ceramic capacitor required for output (see Output Capacitor). ***Reduces output noise (may be omitted if application is not noise critical). Use ceramic or film type with very low leakage current (see Capacitor Characteristics). Figure 34. Basic Application Circuit Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 15 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com Typical Application (continued) 8.2.1 Design Requirements For basic design parameters, see Table 1. Table 1. Design Parameters DESIGN PARAMETER VALUE Input voltage 4.3 V Output voltage 3.3 V Output current 150 mA (maximum) 1 mA (minimum) Output capacitor range 4.7 F 8.2.2 Detailed Design Procedure 8.2.2.1 External Capacitors Like any low-dropout regulator, the LP2992 requires external capacitors for regulator stability. These capacitors must be correctly selected for good performance. 8.2.2.1.1 Input Capacitor An input capacitor whose capacitance is 1 F is required between the LP2992 input and ground (the amount of capacitance may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. NOTE Tantalum capacitors can suffer catastrophic failure due to surge current when connected to a low-impedance source of power (like a battery or very large capacitor). If a tantalum capacitor is used at the input, it must be specified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance is 1 F over the entire operating temperature range. 8.2.2.1.2 Output Capacitor The LP2992 is designed specifically to work with ceramic output capacitors, using circuitry that allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 5 m. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR value which is within the stable range. Curves are provided which show the stable ESR range as a function of load current (see Figure 35). 16 Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 Figure 35. Stable ESR Range vs Load Current The output capacitor must maintain its ESR within the stable region over the full operating temperature range of the application to assure stability. The LP2992 requires a minimum of 4.7 F on the output (output capacitor size can be increased without limit). It is important to remember that capacitor tolerance and variation with temperature must be taken into consideration when selecting an output capacitor so that the minimum required amount of output capacitance is provided over the full operating temperature range. It must be noted that ceramic capacitors can exhibit large changes in capacitance with temperature (see Capacitor Characteristics). The output capacitor must be located not more than 1 cm from the output pin and returned to a clean analog ground. 8.2.2.1.3 Noise Bypass Capacitor Connecting a 10-nF capacitor to the BYPASS pin significantly reduces noise on the regulator output. It should be noted that the capacitor is connected directly to a high-impedance circuit in the bandgap reference. Because this circuit has only a few microamperes flowing in it, any significant loading on this node causes a change in the regulated output voltage. For this reason, dc leakage current through the noise bypass capacitor must never exceed 100 nA, and must be kept as low as possible for best output voltage accuracy. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. 10-nF polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. 8.2.2.2 Capacitor Characteristics The LP2992 was designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the 2.2-F to 10-F range, ceramics are the least expensive and also have the lowest ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 4.7-F ceramic capacitor is in the range of 5 m to 10 m, which easily meets the ESR limits required for stability by the LP2992. One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Most large value ceramic capacitors ( 2.2 F) are manufactured with the Z5U or Y5V temperature characteristic, which results in the capacitance dropping by more than 50% as the temperature goes from 25C to 85C. This could cause problems if a 4.7-F capacitor were used on the output because it drops down to approximately 2.3 F at high ambient temperatures (which could cause the LP2992 to oscillate). If Z5U or Y5V capacitors are used on the output, a minimum capacitance value of 10 F must be observed. A better choice for temperature coefficient in ceramic capacitors is X7R, which holds the capacitance within 15%. Unfortunately, the larger values of capacitance are not offered by all manufacturers in the X7R dielectric. Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 17 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com 8.2.2.2.1 Tantalum Tantalum capacitors are less desirable than ceramics for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-F to 4.7-F range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a Tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. 8.2.2.3 Reverse Input-Output Voltage The PNP power transistor used as the pass element in the LP2992 has an inherent diode connected between the regulator output and input. During normal operation (where the input voltage is higher than the output) this diode is reverse-biased. However, if the output is pulled above the input, this diode turns ON and current flows into the regulator output. In such cases, a parasitic SCR can latch which allows a high current to flow into VIN (and out the ground pin), which can damage the part. In any application where the output may be pulled above the input, an external Schottky diode must be connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP2992 to 0.3 V (see Absolute Maximum Ratings). 8.2.2.4 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 1. PD(MAX) = (VIN(MAX) - VOUT) x IOUT (1) Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance. On the WSON (NGD) package, the primary conduction path for heat is through the exposed power pad to the PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal ground plane with an appropriate amount of copper PCB area. On the SOT-23 (DBV) package, the primary conduction path for heat is through the pins to the PCB. The maximum allowable junction temperature (TJ(MAX))determines maximum power dissipation allowed (PD(MAX)) for the device package. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 2 or Equation 2: TJ(MAX) = TA(MAX) + ( RJA x PD(MAX)) PD = TJ(MAX) - TA(MAX) / RJA (2) (3) Unfortunately, this RJA is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copperspreading area, and is to be used only as a relative measure of package thermal performance. For a welldesigned thermal layout, RJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink. 18 Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 8.2.2.5 Estimating Junction Temperature The EIA/JEDEC standard recommends the use of psi () thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (JT and JB) are given in Thermal Information and are used in accordance with Equation 4 or Equation 5. TJ(MAX) = TTOP + (JT x PD(MAX)) where * * PD(MAX) is explained in Equation 3 TTOP is the temperature measured at the center-top of the device package. TJ(MAX) = TBOARD + (JB x PD(MAX)) (4) where * * PD(MAX) is explained in Equation 3. TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the package edge. (5) For more information about the thermal characteristics JT and JB, see Semiconductor and IC Package Thermal Metrics; for more information about measuring TTOP and TBOARD, Using New Thermal Metrics (SBVA025); and for more information about the EIA/JEDEC JESD51 PCB used for validating RJA, see Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available at www.ti.com. Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 19 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com 8.2.3 Application Curves Figure 36. Load Transient Response Figure 37. Load Transient Response Figure 38. Line Transient Response Figure 39. Line Transient Response Figure 40. Turnon Time Figure 41. Turnon Time 9 Power Supply Recommendations The LP2992 is designed to operate from an input voltage supply range from 2.2 V to 16 V. The input voltage range provides the adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help to improve the output noise performance. 20 Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 LP2992 www.ti.com SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. TI also recommends a ground reference plane either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. 10.2 Layout Examples VOUT VIN 1 IN OUT 5 COUT CIN 2 GND 3 ON/ OFF Power Ground CBYPASS VON/OFF BYPASS 4 Figure 42. LP2992 SOT-23 Package Typical Layout VBYPASS 1 6 CBYPASS Power Ground VOUT COUT 2 GND 5 CIN VON/OFF 3 4 VIN Figure 43. LP2992 WSON Package Typical Layout 10.3 WSON Mounting The WSON package requires specific mounting techniques which are detailed in AN-1187 Leadless Leadframe Package (LLP). Referring to the section PCB Design Recommendations, note that the pad style which must be used with the WSON package is the NSMD (non-solder mask defined) type. The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the amount of additional copper area. Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 21 LP2992 SNVS171J - NOVEMBER 2001 - REVISED JANUARY 2017 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: * AN-1187 Leadless Leadframe Package (LLP) * Semiconductor and IC Package Thermal Metrics * Using New Thermal Metrics (SBVA025) * Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright (c) 2001-2017, Texas Instruments Incorporated Product Folder Links: LP2992 PACKAGE OPTION ADDENDUM www.ti.com 25-Mar-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LP2992AILD-1.5/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L011A LP2992AILD-1.8/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L012A LP2992AILD-3.3/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L014A LP2992AILD-5.0/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L015A LP2992AILDX-3.3/NOPB ACTIVE WSON NGD 6 4500 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L014A LP2992AILDX-5.0/NOPB ACTIVE WSON NGD 6 4500 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L015A LP2992AIM5-1.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFBA LP2992AIM5-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFCA LP2992AIM5-2.5 NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Call TI -40 to 125 LFDA LP2992AIM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFDA LP2992AIM5-3.3 NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Call TI -40 to 125 LFEA LP2992AIM5-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFEA LP2992AIM5-5.0/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFFA LP2992AIM5X-1.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFBA LP2992AIM5X-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFCA LP2992AIM5X-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFDA LP2992AIM5X-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFEA LP2992AIM5X-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFFA LP2992ILD-1.8/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L012A B Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Mar-2021 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LP2992ILD-2.5/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L013A B LP2992ILD-3.3/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L014A B LP2992ILD-5.0/NOPB ACTIVE WSON NGD 6 1000 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L015A B LP2992ILDX-1.5/NOPB ACTIVE WSON NGD 6 4500 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L011A B LP2992ILDX-3.3/NOPB ACTIVE WSON NGD 6 4500 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 125 L014A B LP2992ILDX-5.0/NOPB ACTIVE WSON NGD 6 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L015A B LP2992IM5-1.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFBB LP2992IM5-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFCB LP2992IM5-2.5 NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Call TI -40 to 125 LFDB LP2992IM5-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFDB LP2992IM5-3.0/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM LP2992IM5-3.3 NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Call TI -40 to 125 LFEB LP2992IM5-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFEB LP2992IM5-5.0/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFFB LP2992IM5X-1.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFBB LP2992IM5X-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFCB LP2992IM5X-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFDB LP2992IM5X-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFEB LP2992IM5X-5.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LFFB Addendum-Page 2 LF8B Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Mar-2021 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2021 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2992AILD-1.5/NOPB WSON NGD 6 1000 178.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992AILD-1.8/NOPB WSON NGD 6 1000 178.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992AILD-3.3/NOPB WSON NGD 6 1000 180.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992AILD-5.0/NOPB WSON NGD 6 1000 180.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992AILDX-3.3/NOPB WSON NGD 6 4500 330.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992AILDX-5.0/NOPB WSON NGD 6 4500 330.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992AIM5-1.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5-1.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5-2.5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5-3.3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5-3.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5-5.0/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5X-1.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5X-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5X-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5X-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992AIM5X-5.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2021 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2992ILD-1.8/NOPB WSON NGD 6 1000 180.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992ILD-2.5/NOPB WSON NGD 6 1000 178.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992ILD-3.3/NOPB WSON NGD 6 1000 180.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992ILD-5.0/NOPB WSON NGD 6 1000 180.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992ILDX-1.5/NOPB WSON NGD 6 4500 330.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992ILDX-3.3/NOPB WSON NGD 6 4500 330.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992ILDX-5.0/NOPB WSON NGD 6 4500 330.0 12.4 3.6 3.2 1.0 8.0 12.0 Q1 LP2992IM5-1.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5-1.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5-2.5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5-3.0/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5-3.3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5-3.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5-5.0/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5X-1.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5X-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5X-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5X-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2992IM5X-5.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2021 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2992AILD-1.5/NOPB WSON NGD 6 1000 210.0 185.0 35.0 LP2992AILD-1.8/NOPB WSON NGD 6 1000 210.0 185.0 35.0 LP2992AILD-3.3/NOPB WSON NGD 6 1000 213.0 191.0 35.0 LP2992AILD-5.0/NOPB WSON NGD 6 1000 213.0 191.0 35.0 LP2992AILDX-3.3/NOPB WSON NGD 6 4500 367.0 367.0 38.0 LP2992AILDX-5.0/NOPB WSON NGD 6 4500 367.0 367.0 38.0 LP2992AIM5-1.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992AIM5-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992AIM5-2.5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992AIM5-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992AIM5-3.3 SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992AIM5-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992AIM5-5.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992AIM5X-1.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992AIM5X-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992AIM5X-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992AIM5X-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992AIM5X-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992ILD-1.8/NOPB WSON NGD 6 1000 213.0 191.0 35.0 LP2992ILD-2.5/NOPB WSON NGD 6 1000 210.0 185.0 35.0 LP2992ILD-3.3/NOPB WSON NGD 6 1000 213.0 191.0 35.0 LP2992ILD-5.0/NOPB WSON NGD 6 1000 213.0 191.0 35.0 LP2992ILDX-1.5/NOPB WSON NGD 6 4500 367.0 367.0 38.0 LP2992ILDX-3.3/NOPB WSON NGD 6 4500 367.0 367.0 38.0 LP2992ILDX-5.0/NOPB WSON NGD 6 4500 367.0 367.0 35.0 LP2992IM5-1.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5-2.5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5-3.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5-3.3 SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5-5.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP2992IM5X-1.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992IM5X-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992IM5X-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992IM5X-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2992IM5X-5.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 0.90 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. 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