1. Product profile
1.1 General description
100 W LDMOS power transistor for base station applications at frequencies from
2000 MHz to 2200 MHz.
[1] Test signal: 3GPP; test model 1; 64 DPCH; PAR = 8.4 dB at 0.01 % probability on CCDF; carrier spacing
5MHz.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low Rth providing excellent thermal stability
Designed for broadband operation (2000 MHz to 2200 MHz)
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, rega rd in g Re stri ctio n of Hazard ou s Sub stances
(RoHS)
1.3 Applications
RF power amplifiers for W-CDMA base stations and multi carrier applications in the
2000 MHz to 2200 MHz frequency range
BLF7G22L-100P;
BLF7G22LS-100P
Power LDMOS transistor
Rev. 3 — 2 January 2012 Product data sheet
Table 1. Typical performance
Ty pical RF performance at Tcase = 25
C in a common source class-AB production test circuit.
Test signal f IDq VDS PL(AV) GpDACPR5M
(MHz) (mA) (V) (W) (dB) (%) (dBc)
2-carrier W-CDMA 2110 to 2170 720 28 20 19.1 28.5 34[1]
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 2 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
2. Pinning information
[1] Connected to flange.
3. Ordering information
4. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLF7G22L-100P (SOT1121A)
1drain1
2drain2
3gate1
4gate2
5source [1]
BLF7G22LS-100P (SOT1121B)
1drain1
2drain2
3gate1
4gate2
5source [1]
2
45
3
1
4
35
1
2sym117
4
5
3
21
4
35
1
2sym117
Table 3. Ordering information
Type number Package
Name Description Version
BLF7G22L-100P - flanged LDMOST ceramic package; 2 mounting holes;
4 leads SOT1121A
BLF7G22LS-100P - earless flanged LDMOST ceramic package; 4 leads SOT1121B
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage 0.5 +13 V
Tstg storage temperature 65 +150 C
Tjjunction temperature - 200 C
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 3 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
5. Thermal characteristics
6. Characteristics
7. Test information
7.1 Ruggedness in class-AB operation
The BLF7G22L-100P and BLF7G22LS-100P are capable of withstanding a load
mismatch corr es po nd in g to VSWR = 10 : 1 throug h all ph as es und er the follo win g
conditions: VDS =28V; I
Dq =720mA; P
L= 100 W (CW); f = 2110 M Hz .
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-c) thermal resistance from junction to case Tcase =80C; PL= 20 W 0.36 K/W
Table 6. Characteristics
Tj = 25
C; per section unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS =0V; I
D= 0.6 mA 65 70 - V
VGS(th) gate-source threshold voltage VDS =10 V; I
D= 60 mA 1.5 2 2.3 V
IDSS drain leakage current VGS =0V; V
DS =28V - - 2 A
IDSX drain cut-off current VGS =V
GS(th) +3.75 V;
VDS =10V -12.3-A
IGSS gate leakage current VGS =11 V; V
DS = 0 V - - 200 nA
gfs forward transconductance VDS =10V; I
D=60mA - 530 - mS
RDS(on) drain-source on-state resistance VGS =V
GS(th) + 3.75 V;
ID= 2100 mA -240-m
Table 7. Functional test information
Test signal: 2-carrier W-CDMA; PAR = 8.4 dB at 0.01 % probability on the CCDF; 3GPP test model
1, 1-64 PDPCH; f1= 2112.5 MHz; f2=2117.5MHz; f
3= 2162.5 MHz; f4= 2167.5 MHz;
RF performance at VDS =28V; I
Dq =720mA; T
case =25
C; 2 sections combined unless otherwise
specified; in a class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
PL(AV) average output power - 20 - W
Gppower gain PL(AV) =20W 17.8 19.1 - dB
RLin input return loss PL(AV) =20W - 16 9dB
Ddrain efficiency PL(AV) =20W 24 28.5 - %
ACPR5M adjacent channel power ratio (5 MHz) PL(AV) =20W - 34 28 dBc
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 4 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
7.2 Impedance information
Table 8. Typical push-p ull impedance
Measured load pull data. Typical values unless otherwise specified.
f ZSZL
MHz
2110 1.79 j4.95 2.27 j3.64
2140 2.37 j5.49 2.27 j3.64
2170 2.54 j5.86 1.84j3.57
Fig 1. Definition of transis tor imp e danc e
001aal831
gate drain
Z
S
Z
L
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 5 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
7.3 One Tone CW
7.4 One Tone CW-Pulsed
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 2. Power gain and drain efficiency as function of load power; typical values
0
10
20
30
40
50
60
70
ηD
(%)
ηD
PL (dBm)
36 524840 44
aaa-001309
Gp
(dB)
Gp
0
5
10
15
20
25
30
35
(1) (2) (3)
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 3. Power gain and drain effic ien cy as a function of load power; typical values
0
10
20
30
40
50
60
70
ηD
(%)
ηD
PL (dBm)
36 524840 44
aaa-001310
Gp
(dB)
Gp
0
5
10
15
20
25
30
35
(1) (2) (3)
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 6 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
7.5 1-Carrier W-CDMA
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 4. Power gain and drain efficiency as a function of load power; typical values
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz; f + 5 MHz
(2) f = 2140 MHz; f + 5 MHz
(3) f = 2170 MHz; f + 5 MHz
(4) f = 2110 MHz; f 5 MHz
(5) f = 2140 MHz; f 5 MHz
(6) f = 2170 MHz; f 5 MHz
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 5. Adjacent channe l powe r ratio (5 MHz) as a
function of load power; typical values Fig 6. Peak-to-avera ge ratio as a function of load
power; typical values
0
10
20
30
40
50
60
70
ηD
(%)
ηD
aaa-001311
Gp
(dB)
Gp
0
5
10
15
20
25
30
35
PL (dBm)
36 484440
(1) (2) (3)
aaa-001312
-70
-50
-30
-10
(5)
(4)
(3)
(2)
(6)
PL (dBm)
36 484440
ACPR5M
(dBc)
(1)
PL (dBm)
36 484440
4
2
6
8
PAR
(dB)
0
aaa-001313
(2)
(1)
(3)
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 7 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
7.6 2-Carrier W-CDMA
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 7. Power gain and drain efficiency as a function of load power; typical values
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz; f + 5 MHz
(2) f = 2140 MHz; f + 5 MHz
(3) f = 2170 MHz; f + 5 MHz
(4) f = 2110 MHz; f 5 MHz
(5) f = 2140 MHz; f 5 MHz
(6) f = 2170 MHz; f 5 MHz
VDS = 28 V; IDq = 720 mA.
(1) f = 2110 MHz
(2) f = 2140 MHz
(3) f = 2170 MHz
Fig 8. Adjacent channe l powe r ratio (5 MHz) as a
function of load power; typical values Fig 9. Peak-to-avera ge ratio as a function of load
power; typical values
0
10
20
30
40
50
60
70
ηD
(%)
aaa-001314
Gp
(dB)
0
5
10
15
20
25
30
35
PL (dBm)
36 484440
(1) (2) (3)
aaa-001315
-70
-50
-30
-10
PL (dBm)
36 484440
ACPR5M
(dBc)
(6)
(5)
(4)
(3)
(2)
(1)
aaa-001316
PL (dBm)
36 484440
PAR
(dB)
0
2
4
6
8
10
(3)
(2)
(1)
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 8 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
7.7 Test circuit
[1] American Technical Ceramics type 100A or capacitor of same quality.
[2] American Technical Ceramics type 800B or capacitor of same quality.
Printed-Circuit Board (PCB): Taconic RF35; r = 3.5; thickness = 0.76 mm; thickness copper plating = 35 m.
See Table 9 for a list of components.
Fig 10. Component layout for class-AB production test circuit
aaa-001317
50 mm
60 mm
15 mm
15 mm 18.5 mm
18.5 mm
C14
C8
C3 C1
C9 C11
C6
C10
C7
C12
C13
C4 C2
R1
C5
R2
Table 9. List of components
For test circuit see Figure 10.
Component Description Value Remarks
C1, C2, C9, C10 multilayer ceramic chip capacitor 8.2 pF [1]
C3, C4, C6, C7 multilayer ceramic chip capacitor 1 FMurata
C5, C8 multilayer ceramic chip capacitor 33 pF [2]
C11, C12 multilayer ceramic chip capacitor 0.1 FMurata
C13, C14 electrolytic capacitor 1000 F; 50 V
R1, R2 Chip resistor 5.1 Vishay Dale 0805
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 9 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
8. Package outline
Fig 11. Package outline SOT1121A
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1121A 09-10-12
10-02-02
Flanged LDMOST ceramic package; 2 mounting holes; 4 leads SOT1121A
E1
Q
E
c
D
A
F
D1
A
B
C
q
e
H1
U1
U2
H
Cw2
b
Aw1B
p
2
1
4
5
3
sot1121a_po
Unit(1)
mm max
nom
min
4.75
3.45
3.94
3.68
0.18
0.10
20.02
19.61
19.96
19.66
9.53
9.27
1.14
0.89
19.94
18.92
3.38
3.12
9.91
9.65 0.25
A
Dimensions
bcDD
1EE
1
9.53
9.27
FHH
1
12.83
12.57
pQ
(2)
1.70
1.45
q
27.94
U1
34.16
33.91
U2w1
0.51
inches max
nom
min
0.187
0.136
0.155
0.145
0.007
0.004
8.89
e
0.35
0.788
0.772
0.786
0.774
0.375
0.365
0.045
0.035
0.785
0.745
0.133
0.123
0.39
0.38 0.01
0.375
0.365
0.505
0.495
0.067
0.057 1.1 1.345
1.335 0.02
w2
0 5 10 mm
scale
Note
1. millimeter dimensions are derived from the original inch dimensions.
2. dimension is measured 0.030 inch (0.76 mm) from the body.
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 10 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
Fig 12. Package outline SOT1121B
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1121B
sot1121b_po
09-10-12
09-12-14
Unit(1)
mm max
nom
min
4.75
3.45
3.94
3.68
0.18
0.08
20.02
19.61
19.96
19.66
9.53
9.27
1.14
0.89
19.94
18.92
9.91
9.65
A
Dimensions
Note
1. millimeter dimensions are derived from the original inch dimensions.
2. dimension is measured 0.030 inch (0.76 mm) from the body.
Earless flanged LDMOST ceramic package; 4 leads SOT1121B
bcDD
1EE
1
9.53
9.27
FHH
1
12.83
12.57
Q
1.70
1.45
U1
20.70
20.45
U2
inches max
nom
min
0.187
0.136
0.155
0.145
0.007
0.003
8.89
e
0.35
0.788
0.772
0.786
0.774
0.375
0.365
0.045
0.035
0.785
0.745
0.39
0.38
0.375
0.365
0.505
0.495
0.067
0.057
0.815
0.805
0.25
0.01
0.51
0.02
w2w3
0 5 10 mm
scale
D
H1
U1
A
F
D1D
E1
U2
H
w3
Dw2
Q
E
c
5
2
1
4
3
e
b
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 11 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
9. Abbreviations
10. Revision history
Table 10. Abbreviations
Acronym Description
3GPP Third Generation Partnership Project
CCDF Complementary Cumulative Distribution Function
CW Continuous Wave
DPCH Dedicated Physical Channel
ESD ElectroStatic Discharge
LDMOS Laterally Diffused Metal Oxide Semiconductor
LDMOST Laterally Diffused Metal Oxide Semiconductor Transistor
PAR Peak-to-Average pow er Ra ti o
PDPCH Transmission Power of Dedicated Physical Channel
RF Radio Frequency
VSWR Voltage Standing Wave Ratio
W-CDMA Wideband Code Division Multiple Access
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BLF7G22L-100P_BLF7G22LS-100P v. 3 20120102 Product data sheet - BLF7G22L-100P_BL
F7G22LS-100P v.2
Modifications: •The status of this document has been changed to Product data sheet.
•Figure 1 on page 4: figure has been changed.
BLF7G22L-100P_BLF7G22LS-100P v.2 20111110 Preliminary data sheet - BLF7G22L-100P_BL
F7G22LS-100P v.1
BLF7G22L-100P_BLF7G22LS-100P v.1 20110519 Objective data sheet - -
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 12 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
11. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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full information. For detailed and full informatio n see the relevant full data
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data sheet shall define the specification of the product as agr eed between
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Customers are responsible for the design and ope ration of their applications
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
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Characteristics sections of this document is not warranted. Constant or
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
BLF7G22L-100P_BLF7G22LS-100P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 2 January 2012 13 of 14
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
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are the property of their respect i ve ow ners.
12. Contact information
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For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLF7G22L-100P; BLF7G22LS-100P
Power LDMOS transistor
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 January 2012
Document identifier: BLF7G22L-100P_BLF7G22LS-100P
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
13. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 3
7.1 Ru ggedness in class-AB operation . . . . . . . . . 3
7.2 Impeda nce information. . . . . . . . . . . . . . . . . . . 4
7.3 One Tone CW. . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.4 One Tone CW-Pulsed. . . . . . . . . . . . . . . . . . . . 5
7.5 1-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 6
7.6 2-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 7
7.7 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
9 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
11.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
11.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
11.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
11.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12 Contact information. . . . . . . . . . . . . . . . . . . . . 13
13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14