OKI Semiconductor MSM6262-xx DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER GENERAL DESCRIPTION The MSM6262-xx is a dot matrix LCD controller which is fabricated by OKI's low power consumption CMOS silicon gate technology. In combination with 8-bit microcontroller, the MSM6262-xx can control the dot matrix character type LCD module. The MSM6262-xx consists of 48-dot common driver, display data RAM, character generator RAM, character generator ROM and control circuit. The MSM6262-xx is provided with an serial data transfer output. So, maximum of 160 characters can be controlled by MSM6262-xx by using together with the MSM5259,the MSM5839C or the MSM5260. FEATURES Easy interface with 8-bit microprocessor or 8-bit microcontroller * Dot matrix LCD controller /48-dot driver for three different font configuration (5x7 dots, 5x 11 dots and 5 x 12 dots) Max. 160 characters can be controlled Display RAM ... 160 x 9-bit * On-chip character generator ROM (CGROM) for 256 different characters 5x 7 dots... 128 characters 5x11 dots... 96 characters 5x12 dots... 32 characters * On-chip character generator RAM (CGRAM) of 32 x 8-bit for 2-different character fonts 5x 8dots.. 4 kinds 5x12dots... 2 kinds Under-line function Shift function for g, i, p,q and y Selectable driving duty Duty Font Configuration (dot) Cursor Display (Characters x line) 1/16 5x 7(5x 8) o 80x2 1/24 5x11 (5x 12) oO 80 x2 1/32 5x 7(5x 8) oO 40x4 1/48 5x 11 (5x 12) O 40x4 * Package 80-pin plastic QFP (QFP80-P-1420-BK) (Product name : MSM6262-xxGS-BK) 362M 6724240 0023261 533MSM6262-xx OKI Semiconductor BLOCK DIAGRAM 1d Asna NO bASNa 8PINOD - LWOD o+4 er 4a avor dd ~ | aaoa SA 00 oes JOUBAUOS [BLAS / ||BLg <o PA aBe}|0A r ~o 1A | Sumup aot 7 ir bey jonuos sug 9SZ Asng z ualyguny suq.089' LL (VH99) els aul|-Japun (WoOHD9) WOH WV +o 21531 yung Joyesaua 1aypereyy soyeraueb L1Sat Josuny Jaygerey9 (ua) 16 28d - Jaap 8? |} I ij g { 8 zed 3 ad - odd jeubis lyeysi6e1 om NOW wus } 6 8 -WO0d Nq-8y [~? WW 8 Jayyng oy 4) inding ou! 3 10-6 X 091 g | andy [<> HAY ve (wyyaa) $0 Wid eyep Aedsiq _ 5 + salias Qg/sallas 99 f epoaepl*7 aa von} 6 ually ? Lisid Fonaysuy Loniysuj 8 bs | | ~= 080 L Joyeseue Guywiy | (90) Jalunos ssazppy +_~ 2980 ~Z7 b0S0 o 1, 363 ME 6724240 0023262 47TMSM6262-xx OKI Semiconductor INPUT AND OUTPUT CONFIGURATION Input pin Voo To the inside of the device Applicable pin; OSC1, 68 series/80 series, CS R/W (WR), E (RD) AO, Al Vop Voo To the inside of the device Applicable pin; RESET input /Out put pin From the inside of the device To the inside of the device Applicable pin; OSC2, OSC3 Voo Vp To the inside of of the device Vbo j [~ From the inside of the device Applicable pin; DBO - DB7 364 MB 6724240 0023263 JObOKI Semiconductor MSM6262-xx Output pin From the inside of the device Applicable pin; CP, LOAD, DF, DO, BUSY1 OUT, BUSY2 OUT MP 6724240 0023264 242 mm a A aMSM6262-xx OKI Semiconductor PIN CONFIGURATION (TOP VIEW) SESIYSSSRSSRSBRSR SBSES522 22222222222 8888888 S8S8S88ESES8S8 SPIRE elel IRIE ell is [sll] com46 [7 [64] COM 29 com 47 [2] [63] COM 28 com 48 [3] [62] COM 27 Vss (GND) [_4] [61] COM 26 osci [4] [60] COM 25 oscz [3] [58] COM 24 0sc3 [7 [58] COM 23 TEST1 [Bl [57] COM 22 Test2 [9] (56] COM 21 TESTS [10 155} COM 20 RESET [ti! [54] COM 19 68 series/80 series [12] 53] COM 18 ts G3 [52] COM 17 E(RD) [74] [si] COM 16 RAV (WA) [5 [50] COM 15 AQ [49] COM 14 Al G7] [48] COM 13 peo [78] [47] COM 12 pBt Lg] [46] COM 11 DB2 [BO [45] COM 10 be3 [21] [aa] COM 9 pB4 [22| 143] COM 8 pps [23] C [42] COM 7 ope [24] [41] COM 6 FERRER EBB BESSSSR E5585 5272 = 8888s BUSY 1 OU 80-Pin Plastic QFP 366 Me 6724240 002e32bS 165OKI Semiconductor MSM6262-xx PIN DESCRIPTIONS Symbol Type Description OSC1 v0 Oscillation connection pins 0SC2, OSC3 RESET | Reset pin 68 series/80 series I Selection pin for either 68 series CPU or 80 series CPU cs | Chip select pin. By setting CS at L" level, MSM6262-xx iS Set at selecting condition. RW (WR) | RW pin of 68 series CPU shall be connected to this pin, while WR pin shall be connected to this pin in case of 80 series CPU. E (RD) I E pin of 68 series CPU shall be connected to this pin, while RD pin shall be connected to this pin in case of 80 series CPU. AO, Ai | The address bus of CPU shall be connected to these pins. Instruction code is set by these pins. DBO - DB7 V0 The data bus of CPU shall be connected to these pins. These pins are used to set the data of the instruction or to read the data. TESTI - TEST3 Test pins. Normally these pins should be set at Vs or open. Von. Vss _ Voltage supply pins. Vpp is also used for the common bias voltage level to drive the LCD. V1, V4, V5 _ Common bias voltage input pins to drive the LCD DO 0 Seriai data output pin for SEGMENT drivers CP 0 Clock pulse output pin. The clock output from this pin enables the character pattern data, which is output from DO, to input to the SEGMENT drivers. LOAD 0 Load signal output pin. The character pattern data to the SEGMENT drivers, which was output from DO and CP, is loaded to the LCD output of the SEGMENT drivers, synchronized with the COMMON signal, DF 0 B-type AC signal output pin to drive the LCD COM1 - COM48 0 COMMON signal output pins to drive the LCD BUSY1 OUT 0 This pin shows the internal condition of MSM6262-xx. "H' shows that MSM6262-xx is in internal operation, while "L" shows that MSM6262-xx is ready to receive the instruction from the CPU. BUSY2 OUT 0 This pin shows that MSM6262-xx is in internal operation based on the instruction from the CPU, or MSM6262-xx is in display revising operation based on the instruction from the CPU. "H' shows that MSM6262-xx is in internal operation, while "L" shows that the display on the LCD has been established and the MSM6262-xx is ready to receive an instruction. ME 6724240 0023266 015 367 TN &oUOE oc cc e qc "i ttt! #!_ eeMSMG6262-xx OKI Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Applicable Pin Supply Voltage Vpp Ta = 26C -0.3 to +7.0 V Vop - Vss Supply Voltage Vop - 12 to for Driving LCD Via Ta= 25C Vop + 0.3 v Vials osc RESET 68 series / 80 Input Volt V Ta = 25C 0.3 to Vpp + 0.3 V series nput Voltage IN as -0.3 to Vpp + 0. TS,A0.At RW (WR) E (RD) DBO - DB7 Power Dissipation Pp Ta = 25C 500 mW _ Storage Temper- ature Tste _ 55 to +125 _ RECOMMENDED OPERATING CONDITOINS Parameter Symbol Condition Range Unit Applicable Pin Supply Voltage Vpp - 451055 Vv Vpp - GND 1/45 bias 3.0 to 11 V LCD - Driving Voltage oy 1/6, 1/7 bias 4.0 to 11 V Von - Vs 1/8 bias 45 to it V Operating Temperature Top = -20 to +75 C Note: Refer to *3 in the section, DC Characteristics, concerning bias. 368 Me 6724240 0023267 TS)OKI Semiconductor MSM6262-xx ELECTRICAL CHARACTERISTICS (Von = 4.5 to 5.5V , Ta = -20 to +75C) DC Characteristics Parameter Symbol Condition Min. Typ. | Max. | Unit | Applicable Pin oe _ _ CS, R/W (WR) H" Input Voltage Vins 2.2 Voo V E (RO), AO.AI "L" Input Voltage Vict ome -0.3 0.7 V DBO - DB7 'H Output Voltage Vou 1o = -250pA 24 _ _ V DBO - DB7 "L" Output Voltage Voit Ip = 1.8mA _ 0.4 V "H" Input Voltage Vine _ Vpp-0.8 | Voo V Ci "L" Input Voltage Vite _ -0.3 _ 0.8 V 68series/80series "H" Output Voltage Vone Ip = -500pA 0.85Vpp | _ V DO,LOAD, "L' Output Voltage | Vows lo = SOOpA |015Vpp) Vv | DF "H Output Voltage | Von lo =-1mA 0.85Vpo | _ V cP L" Output Voltage Vos lo= 1mA _ |0.15Vpp H" Output Voltage Vona lo = -100A 2.4 _ _ V BUSY1 OUT L Output Voltage | Vou io = 1.6mA _ | 04 | v_ | BUSY2 OUT COM Voltage Drop | Vcom | to=+50vA ') | | 29 | v | comt-conas "H | Vine V _ 1 A | CSR/W (WR) H* Input Current 1LH1 In = Vo I E (RD AAT "L" Input Current hu Vin = Vsg _- _ 1 HA pt 68 Series/ Vop = 5V, *2 Ipp1 fosc = S00kHz _ _ 1.6 mA Current RC oscillator Consumption Voo=5V.*2 Vop lppe fin = 500kHz | 15 | mA | external oscillator +3| bias | 30 | | 11 V LCD Drivin 16~1/7 Voltage Vico | pp-Vsi pias 4.0 |} Wey Vio] Va. Va Vs 1/8 bias 45 _ 11 "H Input Current HLH Vin = Vop = 2 pA RESET "L' Input Current lie Vin = Vss,Vpp = 5V 8 -20 | -60 pA I. This is applicable to the voltage drop which is caused between Vpp, V1, V4, V3and COM1 ~COM48 when a current of 501A is flowed in/out to/from all of COM1 - COM48. (When the output level is either Vpp or Vj, it should be applied only when the current flows in. When the output level is either V4 or V3, it should be applied only when the current flows in. In this case, +5V is applied to Vpp and Vj, while -6V is applied to V4 and V3.) *2. This is applicable to the current which flows in to Vpp under following conditions. Vop = 5V, Vgg = OV, Vi = 2.8V, V4 = -3.8V, V5 = -6V, No load, No interface with CPU *3. V1 to V5 should be set at as follows. 369 M@ 6724240 00232b8 998 a aMSM6262-xx OKI Semiconductor ug ot ms 2 lines 4 lines Terminal Queation 5x8 5x12 5x8 5x12 1 V4 Vop - + Vico Vpp - + Vico Von - + Vico Vo ~~ Vico 7 V4 Vp0 - 4 Vico Von - 5 Vico Vpn - $ Vico Vop - -> Vico 5 6 7 8 V5 Vop - Vicp Vpp - Vico Vpp - Vico Vop - Vico Vicp = LCD driving vottage AC Characteristics (Vpp = 4.5 to 5.5V,, Ta = -20 to +75C) Parameter Symbol Condition Min. Typ. | Max. | Unit | Applicable Pin Input Frequency fin *1,*2) 300 500 | 700 kHz Input Clock Duty fouty *2) 45 50 55 % Input Clock Fall . osci Time tr 2 _ _ 100 ns Input Clock Fall . Time tt 2 _ _ 100 ns RC Oscillation . Frequency for 3} 300 | 500 | 700 | kHz | OSC1,2,3 H" input Current | Vin=V _ ~ 1 A p ILH3 a i Yu DBO - DB7 "L" Input Current | Is Voo = 5V 45 | -120 | -250 | pA *] 3 Open 4 0503 ee Osc3 Open + sce Ry = 39k + 5% Ry osce Cy = 22pF + 10% WN (Keep the wiring from 0SC1, 0SC2, and osc OSC3 to Ry and Cy as short as possible.) C Oscillation source OSC1 | . Ty 0, toy pg Te * 1% 370 MB 4724240 0023269 62chOKI Semiconductor MSM6262-xx TIMING DIAGRAM Interface with 80 Series CPU (Von = 4.5 to 5.5V, Ta = -20 to +75C) Parameter Symbol Min. Max. Unit Address Set-up Time tsai 110 _ ns CS Set-up Time tsag 100 ns WR'L" Pulse Width twwr 320 ns RD 'L" Pulse Width twrp 320 _ ns WR, RD 'H" Pulse Width twH 210 _ ns Address Hold Time tHat 25 _ ns CS Hold Time thag 25 = ns Data Set-up Time tswo 300 ns Data Hold Time (Write operation) tywo 20 ns WR, RO Fall Time tt - 25 ns WR, RD Rise Time ty = 25 ns Data Delay Time {sap _ 190 ns Data Hold Time (Read operation) tuRD 0 _ ns Busy Output Delay Time ten _ 410 ns 371 Mi 6724240 0023270 Sub aMSM6262-xx OKI Semiconductor Write operation AOA f WH tsa1 tat es Vit VIL igap | twwr tyaa (WR) | ~ Rw Yt a vit i tt the tswo tuwo 080 - 087 ut Valid data ue x tgp BUSY 1 OUT, BUSY 2 OUT - Vou Read operation oat UE iE tsat tHat ts Vir *K Vit tsap | fwep 1 | tHA2 twr E (RD) _ 1 WE Vi tf lee tr sro tuao DBO - DB? i Valid data vor Refer to the chapter of DC characteristics for the definition of Vi, ViL. Vou and VoL. 372 MB 6724240 0023271 44cOKI Semiconductor MSM6262-xx interface with Z80 280 MSM 6262-xx Vss | 68 series/80 series RD - > ERD) WR ) >_ Rw ar) TORO Ag - Ats Address * tS Decoder * AO, Al DBo - DB DBO - DB? * Pull-up resistors of 50 k are required when the output of CPU becomes high impedance. 373 ME 6724240 0023272 315 AESE-'CTCSCiCi(i(<iw lll eeeMSM6262-xx OKI Semiconductor interface with 80C49 MSM 80049 MSM 6262-xx Vsg = 68 series/80 series WR RW (WR) ALE yd DBo - DB7 STB 8282 | PZp- PZe Address |. | | Decoder + AO, Al DBO - DB7 * Pull-up resistors of 50 kQ2 are required when the output of CPU becomes high impedance. Interface with 80C51 MSM 80051 MSM 6262-xx Veg | 68 series/80 series RD E (RD) WR RW (WR) ALE f PQo - PO? STB 8282 PZ, - PZ Address |, | (5 oe Decoder * | AO, Al DBO - DB7 * Pull-up resistors of 50 kQ are required when the output of CPU becomes high impedance. 374 Mmm 6724240 0023273 255OKI Semiconductor MSM6262-xx Interface with 68 Series CPU (Vpp = 4.5 to 5.5V, Ta = -20 to +75C) Parameter Symbol Min. Max. Unit Cycle Time tc 500 _ ns Address, RAW Set-up Time tei 100 _ ns CS Set-up Time tee 90 ns E signal "H" Pulse Width tw 220 ns E signal "L" Pulse Width tL 210 _ ns Address, RAW Hold Time tat 20 _ ns CS Hold Time ta2 20 _ ns Data Set-up Time t 225 _ ns Data Hold Time (Write operation) ty 30 _ ns E signal Rise Time t; - 25 ns E signal Fall Time th _ 25 ns Data Delay Time tp _ 180 ns Data Hold Time (Read operation) to 10 _ ns Busy Output Delay Time teo _ 410 ns 375 M@ 6724240 0623274 19,MSM6262-xx OKI Semiconductor Write operation AO, Al RW (WR) E (RD) 080 - DB? Valid | data ts Vit Busy 1 OUT, Busy 2 OUT Read operation AO, At PW (WR) E (RD) DBO - DB7 Valid | data ict Vit Vit Refer to the chapter of DC Characteristics for the definition of Viy. ViL. Von. and VoL. 376 Me 6724240 OOese75 Oe}OKI Semiconductor MSM6262-xx Interface with 6809 6809 MSM 6262-xx 0 -~ Von =~ 68 series/80 series E ~ *| E (RD) RW * R/AW(WR) NI . Address s Ao Ats decoder * AO, Al DBo - DB7 DBO - DB7 * Puil-up resistors of 50 kQ are required when the output of CPU becomes high impedance. | | | | 377 MH 6724240 0023276 Thy E'S Ciiiiiistll oe _ _____ aeMSM6262-xx OKI Semiconductor Interface with Segment Driver (Vpp = 4.5 to 5.5V, Ta = -20 to +75C, fosc = S5QQkHz) Parameter Symbol Min, Max. Unit Clock "L" Pulse Width tLwicp) 400 ns Clock "H Pulse Width twicp) 400 _ ns Do Set-up Time {setup 200 _ ns Do Hold Time tHoLp 200 _ ns LOAD, Clock Set-up Time toL 200 _ ns LOAD, Clock Hold Time tie 100 _ ns LOAD, H Pulse Width tHWiL) 400 _ ns DF Delay Time tu -600 500 ns 00 LOAD DF Refer to the chapter of DC Characteristics for the definition of Viy, Vit, Von, and VoL. 378 : Me b7e4eh40 OOese7? ITOOKI Semiconductor MSM6262-xx Reset Waveform (Vop = 4.5 to 5.5V, Ta = -20 to +75C) Parameter Symbol Min. Max. Unit L Input Time when power is on tari 0.25 _ ms L Input Width when in operation trlw 0.5 _ ms Rise Time tare 0.5 _ ms Voo tRR2 Viq ESET Vi tRLW Refer to the DC Characteristics for the definition of Vy, Vit, Vou, and VoL. 379 ME 6724240 0023278 437 oeMSM6262-xx OKI Semiconductor FUNCTIONAL DESCRIPTION 1. Instruction Register (IR) and Data Register (DR) The MSM6262-xx has two registers, instruction register (IR) and data register (DR). IR is used to store the address code or instruction code of display data RAM (DD RAM) or character generator RAM (CG RAM). This register can be written by the CPU, but can not be read out by the CPU. DR is used to store the data to write into (or read out) the data to/from DD RAM or CG RAM. The data written into DR by the CPU is automatically written into the DD RAM orCG RAM. When an address code is written into IR, the data of the specified address is automatically transferred to the DR from either DD RAM or CG RAM. By having the CPU subsequently read the DR, it is possible to verify DD RAM or CG RAM data. After the writing of DR by the CPU, the DD RAM or CG RAM of the next address is selected to be ready for the next CPU writing. Likewise, after the reading operation of the CPU, DD RAM or CG RAM data of the next address is transferred to the DR, when CPU is ready for the next reading operation. 2. Busy Flag (BF) When the output of BUSY 1 OUT is "H", MSM6262-xx is engaged in internal operation. When the output of BUSY 2 OUT is "H", it indicates that MSM6262-xx is engaged in internal operation or MSM6262-xx is engaged in the revising of the display of the first line on the LCD. (Refer to the instruction table.) When the output of BUSY 1 OUT is "H", any input of new instruction is ignored. So, before setting a new instruction, it is necessary to check whether BUSY 1 OUT and BUSY 2 OUT are at"L". 3. Address Counter (ADC) The address counter (ADC) allocates the address for the DD RAM and CG RAM write/read and also for the cursor display. When the instruction code fora DD RAM address or CG RAM address setting is input to IR, after deciding whether itis DD RAM orCG RAM, the address counter code is transferred from IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the ADC increments (or decrements) by 1 automatically as its internal operation. 0 Mi 6724240 0023279 773OKI Semiconductor MSM6262-xx 4. Timing Generator Circuit This circuit generates the timing signal for the internal operation by CPU's instruction as well as to operate the internal circuit of DD RAM, CG RAM, CG ROM and so forth. It also generates the transfer signal to the SEGMENT driver (MSM5839C or MSM5259). The internal operation accessed by the CPU and internal operation for LCD display is independent. So, blinking on the LCD, other than the corresponding display of the newly written data, does not occur even when the data is written from the CPU to the DD RAM. 5. Display Data RAM (DD RAM) DD RAM is used to store the 8-bit character code (refer to Table 2) and 1-bit under-line data. The address of DD RAM corresponds to the display position on the LCD. The correspondence is described below. DD RAM address (set to ADC) is described as hexadecimal. DB7 DBs DBs DB, DB3 OB2 DBy DBo aoe [we] TT |] u____-,- / AN ~ Hexadecimal Hexadecimal Example: When DD RAM address is 3A LefetTH{T ata [ipa ie Fe 3 A (1) Relation between DD RAM and display position in 2-lines display mode igit Ps 2 3 4 5 ---+ 79 80 Display position Istline | 00 | 01 | 02 | 03 | 04 --- 4E | 4F 17 DD Ra aaress 2ndtine | 80 | 81 | a2 | 33 | 84 --- ce | cr (hexadecimal) Note: The address of the last digit of the first line and the first digit of the second line does not have any continuity. When 2 pieces of MSM5839C (or MSM5259 ) are connected to MSM6262-xx, 32 characters can be displayed from the first digit to the 16th digit. Digit 1 2,3 4 5 6 7 8 9 10 11 12 13 14 15 16 Istline | 00 | 01 | 02 | 03 | 04] 05] 06 | 07] 08 09 | 0A} 0B} OC | 0D] OE | OF 2nd line | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87/ 88 | 89 | 8A| 8B BC! BD! BE! BF MSM5839C (1) MSMS8396 (2) or MSM5259 (1) MSM5259 (2) MB 6724240 0023280 455 381 a aaaMSM6262-xx OKI Semiconductor When the display is shifted by an instruction, the relation between the DD RAM address and the display position becomes as follows. (Shift to right direction) Digit 1 2 4 5 6 7 8 9 10 11 12 13 #14 15 16 Istline | 4F | 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | OA) OB} OC; OD| OE 2nd tine | CF | 80 | 81 | 82 | 83 | 84 | 85 | 86| 87 | 88 | 89 | 8A| 8B} 8C| 8D| 8E X JX / MSM5839C {i MSM5839C 5 or MSM5259 (1) MSM5259 (2) -~ A. r Ne Istline | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08; 09 | CA| OB | OC | OD OE | OF | 10 2nd line | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88| 89 | 8A) BB} 8C | 8D| SE} BF; 90 (Shift to left direction) The maximum DD RAM capacity of MSM6262-xx is for 160 characters. So, maximum 10 pieces of MSM5839C (or MSM5259) can be connected in case of 2-lines display mode. Digit 12 3 4 5 67 8 9 10 11 12 12 14 15 16 17 18 ---~ 73 74 75 76 77 78 79 80 tstline | 00 | 01 | 02 | 03 104 | 05 | 06 | 07 | 08 | 09) 0A] OB) OC | oD} OE | OF | 10] 11] -- - | 48] 49] 4A] 4B] 4C | 4D] 4 | 4F 2nd line {go | a4 | a2 | 93] 84 | 85 | 86 1 87 | 88190] BA} 8B/ 8C | BD] BE | BF] 90) 91; --- | CB) Ca] CA) CB} CC] CD) CE | CF XQ J - w AN - _? MSM5839C (1) MSM5B396 (2) MSMS58396 (3)-(9) MSMS5839C (10) or _MSM5259 (1) MSM5259. (2) MSM5259 (3)-(9) MSM5259 (10) (2) Relation between the DD RAM and display position in 4-line display mode Digit 1 2 3 4 #5 --- 39 40 Display position ist line | 0O | O1 | 02 | 03 | 04 a 26 | 27 7 2nd line | 40 | 41 | 42 | 43 | 44 --- 66 | 67 +4 DD RAM address 3rd line | 99 | 81 | 82 | 83 | 84 --- AB | A7 LY (hexadecimal) 4th line | co | ci | C2 | C3 | C4 --- 6 | E7 4 Note: The address of the last digit of the previous line and the first digit of the next line does not have any continuity. 382 MB 6724240 0023281 32l1OKI Semiconductor MSM6262-xx When 2 pieces of MSM5839C (or MSM5259) are connected to MSM6262-xx, 64 characters can be displayed from the first digit to the 16th digit. Digit 1 3.4 5 6 7 8 9 10 11 12 13 14 15 16 Istline | 00 | 4 | 02 | 03 | 04 | 05 | 06 | 07] 08 | 09 | oa OB | 0C | OD | OE | OF end line | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47| 48 | 49| 4A| 4B | 4c | ap/ ae | 4F 3rd line | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 8A] 8B] BC] 8D | BE | oF 4th line | Co | C1 | C2 | 63 | ca | c5) c6| c7/c8 | ca] cal cel ccl co! ce | cr Le Yu MSM5839C (H MSM5839C @) or MSM5259 (1) MSM5259_ (2) When the display is shifted by an instruction, the relation between the DD RAM address and the display position becomes as follows. (shift to right direction) Digit 1 2 3 4 5 6 7 8 9 10 14 12 13 14 15 16 Ist line | 27 | 00 | 01 | 02 | 03 | 047 05 | 06] 07 | 08] 09] cal oB OC | OD } OE 2nd line | 67 | 40 | 41 | 42 | 43 | 44 | 45 | 46/47 | 48] 49 | 4a} 4B] 4c | 40 | 4e 3rd line | A7 | 80 | 81 | 82 | 83 | 84| 85 | 86/87 | 88 | 89 | 8A| 8B | BC! 8D | BE 4th line | E7 | Co | Ci | C2 | 03 | C4] c5| ce] c7 1 c8| col cal cel cc! cp | ce LL S\N. 7 MSMS8356 (1) MSM58396 (2) MSM5259. (1) MSM5259 (2) ist line | 01 | 02 | 03 | 04 | 05 | 06 | 07 | o8 | 09 | oaT0B | oc] OD] OE | OF | 10 2nd line | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48! 49 | 4a [4B | 4c | 4D] 4 | 4F | 50 3rd line | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88| 89 | 8a] 8B | 8c! 8D| BE | BF 90 Ath line | C1 | C2 | C3 | ca) C5 | c| 71 c8) co] cal cel ccl col ce | cr DO (shift to left direction) The maximum DD RAM capacity of MSM6262-xx is for 160 characters.So, maximum 5pieces of MSM5839C (or MSM5259) can be connected in case of 4-line display mode. Digit $2 3 4 5 6 7 B G9 10 11 12 13 14 15 16 17 18 --- 33 34 35 36 37 38 39 40 istline 00 | 01} 02 103 /04 | 05) 06 | a7] 08 {09 | 0A | OB} ac jon {oe |oF {10} 11] - -~ |20 | 21 122 103 24 | 25 | 26 | 27 Qndiine | 40) 41) 42 43 | 44 | 45) 46) 47] 48 | 49 | 4A] 481 4C | 4D aE | 4F js0| 51] - ~- 160 |6t 162/69 | 64| 65/66 67 Sstiine | 80 | 81) 82 183 84 | 85] 86 | 87) 88 |89 | 8A| 8B) 8c | aD | se | sr |90! 91] - -- ;ao lat A2 | A3 | Ad] AS | AG | A7 4stline / CO) C1) C2 )C3 | C4 | C5) C6 | C7} C8 |c9) cA] cBl cc| cD cE j cr | 00] 1] - -- Jeo |e1 | c2 | e9 | Es ES | E6 | E7 Aw - JY JX _ _ _______/ MSM5839C (1) MSMSB39C (2) MSM5B39C (3),(4) MSM5839C (5) or =MSM5259 (1) MSMS259 (2) MSM5259_ (3),(4) MSM5259 (5) ME 6724240 90239282 2b8 m 383MSM6262-xx OKI Semiconductor 6. Cursor/Blink Control Circuit This is the circuit to control the generation of cursor and its blinking. This circuit is controlled by the program of the CPU. The position of the cursor and its blink appears on the position according to the ADC contents, which correspond to the address of DD RAM, For example, when the ADC is set as 07 hex., the position of cursor and its blinking becomes as follows. DB7 --- DBO ac [o[ofofofofifi|t 0 7 2-line display Cursor and its blinking position Digit i239 4 5 67 8 /o 79 80 00 [01 | 02 | 03 | 04 | 05 | 06 | 07'| 08 -~- 4E | 4F 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 --- GE | CF 4-line display Cursor and its blinking position Digit 12 3 4 5 67 8 /e --- 39 40 00 | 01 | 02 | 03 | 04 | 05 | 06 o7t 08 7 26 | 27 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 --- 66 | 67 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 -- 7 A6 | A7 CO} C1 | C2 | C3} C4 | C51 C6 | C7 | C8 7-0 E6 | E7 Note: Cursor display and blinking can be performed even when the CG RAM address is set in the ADC. So, it is necessary to disable the cursor display and blinking when the CG RAM address is set in the ADC. 7. Underline Control Circuit First, whether underline display mode or underline blinking mode has to be set by the CPU. When an instruction to enable the underline function is input from the CPU, the cursor display shifts to the right direction (increment) or left direction (decrement). Display of underline appears (or disappears) on the same position where cursor was displayed. An input of "H" data enables the underline display, while an input of "L" data enables to disappear the display of underline. 8 Character Generator ROM (CG ROM) CG ROM stores the character pattern. MSM6262-xx has 128 kinds of 5 x 7 dots pattern, 96 kinds of 5 x 11 dots pattern and 32 kinds of 5 x 12 dots pattern. The character pattern corresponds to the character code which is written into the DD RAM. The relation between 8-bit character code and character pattern is described in Table 2. When the 8-bit character code of CG ROM is written into the DD RAM, the character pattern of the corresponding character code of the CG ROM is displayed on the LCD position corresponding to the DD RAM address. When all of the upper 4-bit of CG ROM code is "L", CG ROM can be switched to CG RAM. an b7e4240 O623263 1T4OKI Semiconductor MSM6262-xx Table 2 Relation between character code and character pattern 0000 | ooot fo) | Got0 | 0011 @ | @) 0100 | a101 (4) |) O110 | O11 (6) | (7) 1000 (8) 1001 (9) 1010 (a) 1011 (8) 1100 {c) 101 | 1990 | 149 (F) Lower 0000 (0) 0001 a) 0010 (2) 0011 (3) 9100 (4) 0101 (5) 0110 (8) oil (7) 1000 (8) 1001 {9) 1010 (a) 1011 (B) 1100 (c) 1101 (D) 1110 {E) W411 (F) Configuration pd 2 a 0 5X 7dots 385 MH 6724240 0023264 O30MSM6262-xx OKI Semiconductor 8. Character Generator RAM (CG RAM) The CG RAM is used to display user's original character pattern other than CG ROM. The CG RAM has capacity (32 bytes = 256 bits) to write 4 kinds of 5 x 8 dots and 2 kinds of 5 x 12 dots. In displaying the character pattern stored in the CG RAM, CG RAM has to be enabled by an instruction. When CG RAM is enabled, CG ROM code for 16 characters cannot be read out since the CGROM code with all "L on the upper 4-bit is used as CG RAM code. The following describes how to write and read the character pattern to and from the CG RAM. (1) When the character pattern is 5 x 8 dots (Gee Table 3-1) * A method to write character pattern into the CG RAM by the CPU 3 bits of the CG RAM address (0-2) correspond to the line position of the character pattern. 2 bits of the CG RAM address (3, 4) correspond to the lower 2-bit of the character code. First, set increment of decrement by the CPU, and then input CG RAM address. After this, write character pattern data into CG RAM through DBO to DB7 line by line. DBO - DB7 correspond to CG RAM data 0 - 7 in Table 3-1. It is displayed when "H is set as input data and is not display when "L" is set as input data. Since the ADC is automatically incremented or decremented by 1 after the writing of data to the CG RAM, it is not necessary to set the CG RAM address again. The line, the CG RAM addresses 0 - 2 of which are all "H" ("7" in hexadecimal notation), is the cursor position. At the cursor position, the character pattern data is ORed with the cursor and displayed to LCD. For this reason, it is necessary to set all input data that become cursor positions to "L". 0 - 4 bits of CG RAM data are output to the LCD as the display data, however, 5 - 7 bits of CG RAM data are not. But it can be used as RAM because data can be written/read / from it. * A method to display the CG RAM character pattern to the LCD First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is selected only when all of the upper 4-bit of the character code is "L". So, the character pattern of CG RAM is displayed on the LCD position, corresponds to the DD RAM address, when the character code shown in Table 3-1 is written into DD RAM. Since the 2 and 3 bits of the character code are regarded as invalid, "K" is displayed when the character code is "01", "05", "09", and "OD". (2) When the character pattern is 5 x 12 dots (See Table 3-2) A method to write character pattern into the CG RAM by the CPU 4 bits of CG RAM address (0 - 3) correspond to the line position of the character pattern. CG RAM address bit 4 corresponds to the bit 1 of the character code. First, set increment or decrement by the CPU, and then input CG RAM address. After this, write the character pattern data into CG RAM through DBo to DB7 line by line. DBo - DB7 correspond to CG RAM data 0 - 7 in Table 3-2. It is displayed when "H" is set as the input data and is not displayed when "L" is set 386 mm 4724240 0023245 T??OKI Semiconductor MSM6262-xx as the input data. Since the ADC is automatically incremented or decremented by 1 after the writing of data to the CG RAM, it is not necessary to set the CG RAM address again. The line, the CG RAM address of which is "0B" or "1B" (hexadecimal), is the cursor position. At the cursor position, the character pattern data is ORed with cursor and is displayed on the LCD. For this reason, it is necessary to set all input data that become cursor positions to "L". The addresses "0" to "B" (hexadecimal) in the bits 0 to 4 of the CG RAM data are output on the LCD as the display data. However, the addresses "C" to F" (hexadecimal) in the bits 0 to 4, and 5 to 7 of the CG RAM data are not output on the LCD. But these CG RAM data can be used as the data RAM so that they can be written into or read out as the RAM. A method to display the CG RAM character pattern on the LCD. First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is selected only when all of the upper 4-bit of the character code is "L. So, the character pattern of CG RAM is displayed on the LCD position corresponding to the DD RAM address, when the character code shown in Table 3-2 is written into the DD RAM. Since the address bits of 0, 2 and 3 are regarded as invalid, the character of "1" is displayed when the character code is "00", "01", "04", "05", "08", "09", "OC" and "OD." (3) A method to read out the CG RAM data First, set the CG RAM address by inputting a CG RAM address set instruction from the CPU, Then, execute the CG RAM/DD RAM data read instruction. The set data of CG RAM address is output from the DBO to DB7. The 8-bit data, read out from the MSM6262-xx, corresponds to the data which is written into the CG RAM. Since the CG RAM address is automatically incremented or decremented by +1 (or-1), the CG RAM read out instruction can be successfully input. It is necessary, however, to set the DD RAMat data transferring condition by executing the DD RAM address set instruction after all of CG RAM data are read out. 387 M! 6724240 0023266 903 a aMSM6262-xx OKI Semiconductor Table 3-1. CG RAM CG RAM DATA DD RAM DATA ADDRESS [CHARACTER PATTERN; CHARACTER CODE 43210)/76543210 76543210 LSB | MSB LSB | MSB LSB LLLLL LiLuH LHL L HH LELLXXLL HLL HLH HHL HHH LHLLL LtuH LHL L HH HLL LLLLXXLH HLH HHL HHH ee HHLLLIX XX L LH LHL L HH LLLLXXHH HLL HLH HHL HHH X: Don't care 388 Me 6724240 O023c45? S4TMSM6262-xx LSB DD RAM DATA 76543210 LLLiXXLX LLLLX XH X LSB | MSB CG RAM DATA 76543210 ADDRESS (CHARACTER PATTERN| CHARACTER CODE LSB | MSB CG RAM 43210 Table 3-2. TFarsrsararitjsxrIi=z JSEEAsrrssrrissurs oH sar rrrsasst sit torT JAuounasnusnousurtrerrjrrirt.s Boros rursaratjirtsit SEDPIGTTIATDAsTrs Joavtrrrss ssa rtrirT soso sgusurrrrlrr6orst at OKI Semiconductor 389 X: Don't care Mi 6724240 0023288 786 MeMSM6262-xx OKI Semiconductor 9. LCD Display Circuit (COM1 to COM48, DO, CP, LOAD, DF) The MSM6262-xx is provided with COMMON signal output. So, maximum 160 characters can be displayed when itis used together with SEGMENT drivers (MSM5259 or MSM5839C). Interface between MSM6262-xx and SEGMENT drivers can be done by using DO, CP, LOAD and DF. The SEGMENT data is serially output from DO pin, synchronized with the pulse which is output from the CP pin. This data, input to the SEGMENT driver, is converted from serial data to parallel data by the latch pulse which is output from the LOAD pin of MSM6262-xx and this converted data is used as the display data. This parallel/serial conversion is performed synchronized with the COMMON signal of MSM6262-xx and LCD display AC signal which is output from DF pin. So, this signal can drive dot matrix LCD panel. 10. Reset Circuit Power-on-reset is required for MSM6262-xx when it is powered-on. So, a capacitor has to be connected between RESET pin and Vsg pin. It is also advisable to connect a diode between RESET pin and Vsg pin when it is required to connect a capacitor of more than 3.3 wF to RESET pin. When the power-on reset circuit normally operates, the busy flags 1 and 2 become at "H" level for about 10 ms after the power-on. During this period, a initialization of MSM6262-xx is performed by following procedures. Display clear CG ROM becomes ENABLE No display shift Increment of ADC 2-line display mode 5 x 8 dots font configuration No display shift for "g","j', "p", "q" and "y" Display off No display of cursor, blinking and underline WON ARON RH 11. Data Bus with CPU MSM6262-xx can be interfaced with 8-bit CPU, such as 6809, Z80, 80C49 and 80C51. When MSM6262-xx is connected with 6809, 68 series /80 series pin has to be connected to Vpp. When MSM6262-xx is connected with 280, 80C49 or 80C51, 68 series /80 series pin has to be connected to Vgg. 68 series /80 series level cannot be switched during MSM6262-xx's opera- tion. It has to be connected with either Vpp or Vss before MSM6262-xx is powered-on. Note: When a reset signal is being input to RESET pin, 68 series /80 series pin's level can be switched. Since 68 series /80 series pin does not have a switching characteristics nor V7 characteristics to have a interface with MCU nor it does not have an anti- chaterring circuit. So, this method is not a recommendable one since MSM6262-xx is initialized when a reset signal is input. 390 me Brekeuo pu23289 ble =OKI Semiconductor MSM6262-xx 80 series CPU data transfer E (RD) \ / ~\ / Ao CS NO BUSY1 DB; Ry _X_/gusyi DR NO BUSY2 DBs Rex BUSY? ORg DBs IRs XK OX cGmBx XX _DRs > DB, Ra XE DBs Ts = DB Ro XX * NOX X__DRe > DB Ry >= OX DBo a a DRX USY1 a Internal peration) ter Internal peration} Write an instruction (IR) Read the busy flag Write the data register (RD) *: Don't care MEL? 242uQ 00e3290 334 mm ~ aMSM6262-xx OKI Semiconductor 68 series CPU data transfer E (RD) /N J \ [\ [_ RWWWRym______~___.s MW At af Nt A NO BUSY1 DBy XR Busy! DRy NO BUSY2 DBs < _ Re BUSY? DRe DBs X_IRs x1 _X <cqmpx<___<_DRs_> DB, xR XOX WD X_X_DRa_ > DBs X_IRs ) a < SX _DRs_> DBy < _IRe xX A/0 DR2 DB IR xX DBo Ro XX xX CUD <___X_DRo_> USY1 a Internal peration) USY2 Internal peration) Write an instruction (IR) Read the busy flag Write the data register (RD) *: Don't care 392 - ME 6724240 0023291 270OKI Semiconductor MSM6262-xx Instruction Table Note 1: In case of 80 series CPU, access to MSM6262-xx is done by WR and RD. So, a bit for part of the read/write code is not required * : DON'T CARE Nott a DB; | 0B, | OB, | OB,| DB; | OB,; DB, | 0B Execution tes Op 1 . a Z $ 3 2 : : Explanation Time (MAX) RW} A, Ay | DB, | OB, | DB, | DB, | OB, | DB, | DB, DA, tosc - 500kHz Display Clear L L L L L L L L L L H lear all ol the display. and set Gacldress of DD HAM in the address 3.22ms counter. Return L L L L L L L L L H | CRIC CRIC = L; Cursor home 1.62ms CRA arriage Return : Under Line L L L L L L L L H UL * UL = 1; Write the underline in the cursor part before executing this instruction. 20us UL = 0; Erase the underline in the. ht cursor part before executing this instruction (S) set whether the Entry Mode Set L L L L L L L H Vo 5 AO diy of the direction of eursor {UD} should be shifted or not. When the data is being written or rad, this operation 20ps is performed. This instruction also set whethar the Character code of DD RAM is used as OG ROM or CG RAM.(A/0} OisplayCursor Shift | L | t FL tk fu feu ut se furl & Io, This instruction shift the cursor and play! AL (ue) GS displa y without chat ging th 20ps DL contants. (S/C, DAL devoL) This instruction set the CG RAM CG RAM address Set L t L L L 4 Ay address. The dara, which will be sent/ 20s S received after the ce RAM address is _sat, is AM dal i L L L N * * This instruction ral followings. Function Set t 4 Fy fe Fr No. ol lines (N). Character toni 20us (F,). Cursor line font (F,), Font shift " of gi pay (Fs) Diaplay Control * . This instruction sat lay t t L H p c 8 uc UB Al al dsp on/olt Hi. tare? tisplay Char. ae on the curs 20ys postion ol onotf ), dering display or ne bacon on/off (UB) ~ CORRWDD RAM t T H WRITE DATA Wie 3 data in either DD RAM or 20ys DD RAM Address cfu le Set DD RAM address. Set Ano The data which is sant/received alter 20ys that is DD RAM data, Read the Under- H L Lf ULD Read following data, lined Data READ DATA Data on the underline, OD RAM or 20s CG RAM data. Read the CG RAM # L H Read the data either from DD RAM DD RAM Data READ DATA Read 20) Read the Address H H L Bog Read ie wae counter contents us Counter Content M FI H H [| BIF | BF] CG | VD 5S | AO] D UD Busy 1 flag (BiF) which shows Read Busy Flag q DO WSMG ae $ intemal operation Busy 2 tiag (B2F} which shows that the Fewsing of display starting ling is ets ID shows whether the data, being transmitted or received. is CG RAM of DD RAM. Ops WD shows the direction ol cursor. S shows the display shift VO shows when the DD RAM charac- ter code is CG RAM character code or CG RAM character cade D shows the all display on/off UD shows underine display onvoft CRC =H : Carnage Return CR/C=L - Cursor home DO RAM : Display data RAM in case of UL=sH Write tinder ling ULel : Underling erase CG RAM: Character generator fosc = yo ay : fon display shit Wel: Decrement RAM d 600 kHz. = : Accompany display shift address. 2 MO-. - CGROMENABLE NO=H CORAM ENABLE xe - DD RAM address it becomes S=H : Biapiey move SCL: Cursor move Ade Address counter which 0 500 UD/RL H: Up/Down move UD/AL = L Lelv/Right move 1s used for both DD 20usxea 0,.0, : ire bitto se the ling to be displayed in the upper-most position RAM and CG RAM D, 1s LSB. 0, is MSB = 16.7ps prot =H yipper. fight move UROL = L. Down-lefl move N H 4 tines Fy =H. 5x11 dots Fy=L : 5x7 dow Feel :5x12dotsor5x 8 dots f =R x 11 dots or 5x7 dots Fy eH: Shiltg.j.p. a. y'tolne FS =L : Character shitt disable Sower position by 1-dot ULD=H : Underline data exist ULD=L_ : No undertine data BIF=H Intemal operation BiF=L Ready to receive instruction B2F=H . Revising the display starting B2F=L :No revision on display fine or internal operation Starting lin CG/DD =H. Transmit or receive CG RAM CG/DD aL: Transinil/Receive of DD RAM _fata_ data MB 6724240 0023292 107 os a ae aMSM6262-xx OKI Semiconductor 12. Instruction Code The instruction code is defined as the signal through which the MSM6262-xx is accessed by the CPU. MSM6262-xx starts its operation upon receipt of the instruction code. The internal processing operation starts with a timing that does not affect the LCD display, so, the busy condition is longer than that of cycle time. In the busy condition, MSM6262-xx does not execute any instruction other than the reading of busy flag. Therefore, the CPU has to verify that busy flag is set at "L" before inputting the instruction code. (1) Display clear A; Ao DBy DBg DBs DBs DB3 DBs DB; DBo Instruction instruction Ta Ti [i Tt Tee [itr te] When this instruction is executed, the LCD display is cleared. When the cursor and blink is being displayed, the blinking position moves to the left end of the LCD. (In case of 2-line or 4-line display mode, it moves to the left end of the first line) All of the DD RAM data becomes "20" (hex), space code, while ADC data becomes "00" (hex.). If display is shifted, it returns to the normal position. Data for underline is re-written as "L" and display turns off. (2) Return e CR/C =L (Cursor Home) A; Ag ODB7 DBg O85 DBy DB3 DBs DB, D8 Instruction ae Fefefefetetule fe fa [ere] When this instruction is executed, cursor and blinking position moves to the left end of the LCD. (In case of 2-line or 4-line display mode, it moves to the left end of the first line) When display is being shifted, the display returns to its original position for both parallely and vertically. ADC becomes "00" (hex.). * CR/C =H (Carriage Return) When this instruction is executed, cursor and blinking position moves to the left end of the line. Ifthe display is being shifted when this instruction was executed, only cursor and blinking position moves to the original position before it was shifted. All bit other than line specifying the bit of ADC will be reset to "00". 394 ME 6724240 9023293 043OKI Semiconductor MSM6262-xx (3) Underline A; Ao OB; DBg DBs DB, DB3 DBo DB; DBo Instruction iia Litctetetetey atu ful. | *: Don't care UL=H (Write underline) When this instruction is executed, the underline appears on the cursor position. Cursor will move to the reght or left if either increment or decrement is specified. UL=L (Erase underline) When this instruction is executed, the underline on the cursor position disappears. Cursor will move to the right or left if either increment or decrement is specified. When this instruction is executed, ADC will be automatically incremented by +1 or decremented by -1. Display is shifted accordingly. (4) Entry mode set Ao DB7 DBg DBs DBg DB3 DB2 DB, DBp Ay struction (tL Ti [te Ti [tl[t [x [mls [ao] I/D (ncrement/Decrement) When this instruction is executed, DD RAM address will be incremented (1/D = "H") or decremented (I/D ="L") by 1, after the character code or underline code is written into (or read out from) the DD RAM. In case of increment, cursor moves to the right, while the cursor moves to the left in case of decrement. It is same in case of writing /reading the data into/from CG RAM. * S (Display shift in case of writing) When S = "H" in case of writing data into DD RAM, display is shifted either to the right or left. When I/D = "H", all display will shift to the left, while it will shift to the right when I/ D="L". So, display of cursor looks being stopped and display itself looks being shifted. In case of reading the data from DD RAM, display shall not be shifted. In case of reading / writing the data from/to CG RAM, display shall not be shifted. In case of S = "L", display shall not be shifted. A/O(CG RAM ENABL/CG ROM ENABLE) When A/O is "L",CG ROM will be enabled, and all CG ROM contets on Table 2 becomes selectable and CG RAM cannot be selected. CG RAM cannot be used as character code for display. But it can be used as data RAM. When A/O ="H", CG RAM is enabled. In case the upper 4-bit of the character code in Table 2 is "00" (hex.), the bit pattern of CG RAM is displayed on the LCD. (CG RAM has a RAM area for 4 kinds of 5 x 8 dots and 2 kinds of 5 x 12 dots) CG ROMis selected when the upper 4-bit of the character code in Table? is "01" -"OF" (hex.). M 6724240 0023294 TaT 395 EEE EEE EEEI OOO eeMSM6262-xx OKI Semiconductor (5) Display /Cursor move A; Ao DB7 DBg DBs DB, DB3 DBz DB, DBo ud/ | Pa} Dy L Je] ubuee H } SiC] ar | WR Instruction code *: Don't care * S/C (display move/Corsor move) This is the bit to select either display or crusor to move. S/C = "H" enables the display movement, while $/C = L" enables the cursor movement. * UD/RL (Upward or Downward move/Right or left move) UD/RL = "H" enables upward or downward move. UD/RL = "L" enables right or left move. Dz, D; Starting line of display) Upward or downward movement is enabled by setting the starting line of display. D, is LSB and D, is MSB. Both D, and Dy is expressed in 2-bit binary data. In case of 2-line mode, only Dy is regarded as valid. Both D; and D2 are regarded as valid data in case of 4-line mode. = 2-line mode = DD RAM Do=*,D,="L Display of the LCD 1st line 1st line 2nd line 2nd line ist line 7 {st line 2nd line 2nd line *: Dont care 396 MB 6724240 0023295 WbOKI Semiconductor MSM6262-xx = 4-line mode = DD RAM D2 ="L", Dy ="L" Display of the LCD Ist line Ist line 2nd line 2nd line 3rd line 3rd line 4th line 4th tine Do ="L", Dy ="H" Ist line Ist line 2nd line 2nd line 3rd line 3rd line 4th line 4th line Do = H, Dy ="L" Ist line 1st line 2nd line 2nd line 3rd line 3rd line 4th line 4th line Do = "H, Dy ="H" Ist line Ist line 2nd line 2nd line 3rd line 3rd line 4th line 4th line 7 ME 6724240 00232956 8S2 mm 9 a a a aMSM6262-xx OKI Semiconductor UR/DL (Up-right move/Down-left move) UR/DL ="H" enables up-right movement. UR/DL = "L enables down-left movement. Combination of bit for Display /Cursor movement is as follwes D. sic OAL cu D1 Explanation L L * Move the cursor to the left by 1 digit * Move the cursor to the right by 1 digit * Move the cursor to the downward by 1 digit * Move the cursor to the upward by 1 digit * Move the display to the left by 1 digit Move the display to the right by 1 digit Set the first line as the display starting line Set the 2nd line as the display starting line Set the 3rd line as the display starting line a2 Set the 4th line as the display starting line a2 TrearTAaTtTTet TH TT TH roeoerTTrTaey--r-Ttaa re xzrererere Tree ee se m= T-ascrT * *: Don't care Note: In the case of 2-line mode, 2 is invalid. (6) CG RAM address set instruction At; A-DBr_DBs DBs DBs DBs DB _DB;_DBo code Fo] ete fet [it [x | Aca | Aca | Ace | Act | Aco | Set the CG RAM address which consists of 5-bit of Acq - Aco. The data which will be transferred after this instruction is set shall be limited to the CG RAM data (character font data). 398 MB 6724240 0023297 795OKI Semiconductor MSM6262-xx (7) Function set Ai Ao DB7 DBs DBs DB, DBs DBp DB, DBo Lit{ttr[n]- [AiR] fs | *: Don't care Instruction code N (4line/2-line) LCD line selection LCD lines L 2-line mode 4-line mode F, Gx 11 dots/5 x 7 dots) When F, = "H", 5 x 12 dots/font is selected. When F, = "L", 5 x 8 dots/font is selected. * F) (Font assignment of cursor line) When F) = "L" and if character code, which has a display dot on the cursor position, is selected, it is displayed on the cursor line of LCD. When F, = "H" and if character code, which has a display dot on the cursor position, is selected, cursor is displayed but the bit on the cursor position is not displayed. In case of CG RAM, however, this function is not applicable and the bit on the cursor position is also displayed. Fs (Font shift of "g, j, p,q y") When F3 = "H", the character font of "g, j, p, q, y" is shifted to the downward by 1-bit. When F3 ="L", display is same as that described in Table 2. This bit is only valid in case of 5x 12 dots/font. Example 3 Fy =U (5x 8 dots/font) 5x11 or 5 x 12 dots font ROM 3dots (7 7 dots | Not displayed Cursor position ~~ a / Cursor 5x7 dots font ROM Mi 6724240 0023296 bes 399 Ce LeMSM6262-xx OKI Semiconductor 3. Fy ="H' (5x 12 dots/font) 5x 11 dots 5x7 dots font ROM font ROM 5x 12 dots font ROM Cursor position + Cursor position 4 Fo='L" Fe ~+ Cursor position 5 Fs="t' mt a] hel ~= Cursor position 6 F3="H (5x 12 dots/font only) Lt T (J Ty - Cursor position - Shift downward by 1 dot MB 6724240 0023299 5SblOKI Semiconductor MSM6262-xx (8) Display control Ay Ao DBy DBg DBs DB, DB3 DBy DB, DBo Letetutolc]s fuluy- [| *: Don't care Instruction code D When D = "H", display on the LCD is enabled. When D = "L", display is disabled. When display was disabled by setting D at "L", character code in the DD RAM does not change. So, when D becomes at "H" again, display is enabled immediately. e Cc When C = "H", cursor display appears. When C = "L", cursor display disappears. * B When B ="H", blinking of character, on the position corresponding to the cursor position, starts. Blinking of all-dot's-on and character (and cursor)-on is performed alternately for every 409.6 ms in case of fosc = 500 kHz and 5 x 8 dots font configuration (every 614.4 ms in case of 5 x 12 dots font configuration) When B = "L", blinking stops. Cursor and blinking can be set simultaneously. * UC When UC = "H", underline is displayed on the cursor position. When UC = "L", underline display is disabled. * UB When UB = "H", blinking of character, on the position corresponding to the underline position, starts. Blinking of character stops when UB = L". Cursor, blink, underline and blinking of character on the underline can be set simultaneously. (9) CG RAM and DD RAM data write Ao DBy DBg DBs DBy DBs DBo DB, DBo Ay struction Lt [Th [ov [oe | 0s [ou | ds | de | on | de | Write the 8-bit data (Diz - Dig) into either CG RAM or DD RAM. Determination of either CG RAM or DD RAM is made by the CC RAM address set or DD RAM address set which shall be set in advance. After the data was written into the RAM, it is incremented or decremented by 1 according to the entry mode of the address. Display shift will be also determined by the entry mode. ME 6724240 0023300 003 401 aaaMSM6262-xx OKI Semiconductor (10) DD RAM address set A: Ao DB7 DBs DBs DBs DBs DBo DB, DB msvmuction H | Lt | Az] Aw | Ais | Au | Als | Ale | An | Alo | This instruction code set the DD RAM address, consists of 8-bit (Aj7 to Ajy). The data which is received after this instruction was set shall be limited to the DD RAM data (character code data). The address code other than below shall not be input. 2-line mode : 1st line 00 - 4F 2nd line 80-CF 4-line mode: 1st line 00 - 27 2nd line 40-67 3rd line 80-A7 4thline COQ-E7 (11) Underline data read At Ag DB7 OBg DBs OB, DBs DB2 DB; DBo mssruction L Tt | uo] Dog | Dos | Dog | Dog | Dop | Dor | Doo | This instruction read under line data, and CG RAM or DD RAM data. Determination of CG RAM or DD RAM is made by the CG RAM address set or DD RAM set which shall be set in advance. The first data read by this instruction is a valid data. Normal data is read out from the second instruction onward if the read instruction was executed continuously. This instruction address will be incremented or decremented by 1 according to the entry mode. Display shift is not, however, performed. Underline data is output to DB7 as either H (when display is on) or "L (when display is off). The MSB of RAM data is not read. RAM data consists of 7-bit (DBO to DB6) 402 MB 4724240 0023301 THT amOKI Semiconductor MSM6262-xx (12) CG RAM and DD RAM data read Ay Ag ODB7 OBg DBs DB, DBs DB. DBy OB instruction | t | H | O07 | Dog] Dos | Dog | Dog | Doz | Dor | Doo | This instruction read the 8-bit data (DO7 to DOg) from either CG RAM or DD RAM. Determination of CG RAM or DD RAM is made by the CG RAM address setor DD RAM address set which shall be set in advance. CG RAM address set instruction or DD RAM address set instruction has to be input just before executing this read instruction. If it is not input, the first output of the data becomes invalid. When this read instruction is performed continuously, normal data is output from the 2nd data onward. In case of DD RAM data read, normal data is output from the first data without inputting the address set under the condition that cursor is moved by the cursor shift instruction. After reading the data, the address is incremented or decremented by 1 by the entry mode. The shift of the display, however, is not performed. (13) Address counter read Ar Ag DB7 DBg DBs OB, DBs DBo DB; DBo Instruction [iy TL [ Aor | Ags | Ads | Ady | Ao3 | Ado | Ady | Ado | code This instruction read the 8-bit data (AO7 to AOo) . Adress counter is determined by the address which shall be set in advance as it is used for both CG RAM and DD RAM. (14) Busy flag read Ar Ag D87 DBs DBs DBy DBs DBo DB; DBo Instruction CG/ code H H | BIF | BaF pD VD; | AO} D | UD BIF (Busy 1 flag) When B1F ="H", MSM6262-xx is engaged in internal operation and next instructionis not accepted until when B1F becomes "L.So, subsequent instruction has tobe input after BIF is confirmed at "L". During B1F = "H", DBs to DBy cannot be determined. B2F (Busy 2 flag) B2F indicates that MSM6262-xx is engaged in its internal operation and it also indicates that the display starting line is under being revised. Instruction contents of B1F and B2F are same other than when setting the starting line of display. B2F = "H" indicates that MSM6262-xx is engaged in its internal operation. B2F = "L" indicates that MAM6262-xx is ready for accepting new instruction. Even when B2F ="H", new instruction can be accepted if BIF = "L", When the starting line of display is revised under this condition, the previous set data about starting line of display becomes invalid and the newly input data about starting line becomes valid. 403 WM 6724240 0023302 586 aMSM6262-xx OKI Semiconductor CG/DD (CG RAM/DD RAM) This bit indicates whether the address counter contents are CG RAM or DD RAM when B1F = "L". CG RAM is selected when CG/DD = "H", while DD RAM is selected when CG/DD = "L". I/D (Increment/Decrement) This is the bit toset the increment or decrement when B1F ="L". Incrementis selected when 1/D ="H", while decrement is selected when I/D = "L". S(Ghift) This is the bit to set the shift condition in the entry mode when B1F ="L". Shift is set when S ="H", while shift is disabled when S = "L. A/O (CG RAM ENABLE/CG ROM ENABLE) The bit indicating that the entry mode set is in CG ROM ENABLE or CG RAM state when BIF = "L". CG ROM is selected when A/O = "L" and CG RAM is selected when A/O = "H". D (Display) This is the bit to indicate whether the display, which was set by display control instruction, is on or off when B1F = "L". The display is on when D = "H" and the display is off when D="L". UD (Underline) This is the bit to indicate the condition of underline or blinking on the underline, both of which were set by display control instruction, when BIF = "L". When UD ="H", either (or both of) underline display or blinking on the underline is being executed. When UD = "L", it indicates neither of underline display nor blinking on the underline is performed. (15) Instruction Initialization 1 Power on. 2 Wait for 15 ms or more after Vpp becomes at 4.5 V. 3 No busy 1 check (Check BIF = "L") 4 Set No. of lines, character font by instruction. (After this stage, function set instruction cannot be input.) 5 No BUSY 1 check 6 Set display-off by inputting display control instruction. 7 No BUSY 1 check 8 Input display clear 9 No BUSY 1 check 10 Set entry mode 11 No BUSY 1 check 12 Set following functions. Display on, Cursor, Blink, Underline Blink on the underline 13 No BUSY 1 check 14 Initialization complete MM 6724240 0023303 812OKI Semiconductor MSM6262-xx APPLICATION CIRCUITS * Interface with MSM6262-xx and LCD driver When Vicp is within the voltage range of Vpp to Vcg, MSM5259 is recommendable as SEGMENT driver. When Vi cp is beyond the voltage range of Vpp to Vss, MSM5839C is recommendable as SEGMENT driver. 1 2-line display mode 5x 7 dots, 2 lines x 16 characters (Note: COM17 - COM48 should be left apen) COM16 CoM 7 COM48 MSM6262-xx mt oe D a BO 1 1 cp cp MSMS259 cp MSM5259 DF LOAD LOAD DF Diy, LOAD OF Dio, MB b?e4240 0023504 759 405 a aMSM6262-xx OKI Semiconductor 2 = 2-line display mode 5x11 dots, 2 lines x 16 characters (Note: COM25 - COM48 should be left open) COM24 COM25 I COM48 cursor MSM6262-xx DO cP LOAD Ae Dl, M52 cp MSM5259 LOAD DF cp MSMS5259 LOAD DF DF Dla Diy 406 Me 6724240 0023305 6915OKI Semiconductor MSM6262-xx 3 4-line display mode 5x7 dots, 4 lines x 16 characters (Note: COM33 - COM48 should be left open) LOD cOM1 COM32 COM33 | COM48 MSM6262-xx DO id 7 DI, C Di, P C cp cP MSM58391 cP MSM5839' DF LOAD LOAD DF Dl, LOAD DF DOz Dlay 407 M@m@ 6724240 0023306 Sel aMSM6262-xx OKI Semiconductor 4 4-line display mode 5x 11 dots, 4 lines x 16 characters LCD cOM1 cOM48 MSM6262-xx nd bo MSM5839C MSM5839C cP cP cP LOAD LOAD OF Dloy LOAD DF Dla 408 MB 6724240 0023307 465OKI Semiconductor MSM6262-xx MSM6262-xx, MSM5839C, Bias circuit connection MSM5839C -5V D029 MSM5839C Dl, cP LOAD OF 5V MSM6262-x @ 6724240 0023308 374 409 0 EOMSM6262-xx OKI Semiconductor Example of bias circuit 1/5 - 1/8 bias example 1. Bias | 1/5 | 146 | 1/7 | 1/8 PR R | 2R | 3R | 4R Vico: LCD driving voltage Voo ER V4 Vics R V2 MSM6262-xx RR |. R to segment V4 driver R Vs i Vee r VR 1/5 - 1/8 bias example 2. Bias | 1/5 | 1/6 | 1/7 | 1/8 RR R | 2R | 3R | 4R Vico: LCD driving voltage Vop Ic : R Vy T Vico R C TeV, MSM6262-xx >RR Le J V3 ; lr sR 0 segment V4 To | driver + sR LC Vs Vee > f VR ==C 410 WM 6724240 0023309 230OKI Semiconductor MSM6262-xx LCD duty and bias No. of line 2-line 4-line Duty - | 146 | 1/24 | 1/32 | 1/48 Bias 1/5 1/6 7? | 1/8 Above are examples of relation between LCD duty and bias. Since it is subject to change, it depends on the characteristics of LCD panel, please use above as a reference value. The value of resistor on bias circuit is determined by the operational margin and power consumption. To make the power consumption lower, the value of resistor has to be bigger and this make the LCD driving output resistance high and it causes the distortion on the LCD driving waveform. In case of large LCD panel, the value of the resistor should be much lower as the LCD capacitance increases. To improve the distortion of LCD driving waveform, to connect a bypass capacitor parallely to the bias resistor, can be useful. But to connect a capacitor of too big value causes the level shift of the bias voltage. So, it has to be determined carefully after checking experimentally. Followings are the reference value. R= 2 to 10kQ Vr = 10 to 50kQ r= 0.2 to2kQ c = 0.0022 to 0.047 LF 411 Me 6724240 0023310 T5e a aaa aaMSM6262-xx OKI Semiconductor LCD Driving waveform COM < CON2 SEG < a rr a 1 frame Duty 16 1/24 1832 1/48 Frame frequency | 78,125Hz 2,08Hz | 78,125Hz | 52,08Hz Note: fosc = 500kHz 412M So6724240 002331) 999 om