Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
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In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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1. General description
The HEF4051B-Q100 is an 8-channel analog multiplexer/demultiplexer with three
address inputs (S1 to S3), an active LOW enable input (E), eight independent
inputs/outputs (Y0 to Y7) and a common input/output (Z). The device contains eight
bidirectional analog switches, each with one side connected to an independent
input/output (Y0 to Y7) and the other side connected to a common input/output (Z). With
ELOW , o ne of the eight switches is se lected (low-impedance ON-sta te) by S1 to S3. With
EHIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. If
break before make is needed, then it is necessary to use the enable input.
VDD and VSS are the supply voltage connections for the digital control inputs (S1 to S3,
and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (Y0 to Y7, and Z)
can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not
exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
Rev. 2 — 11 September 2014 Product data sheet
HEF4051B_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 11 September 2014 2 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
4. Ordering information
5. Functional diagram
Table 1. Ordering information
All types operate from
40
C to +125
C.
Type number Package
Name Description Version
HEF4051BT-Q100 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4051BTT-Q1 00 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Fig 1. Functional di agram
001aac277
LOGIC
LEVEL
CONVERSION
11
16
VDD
13 Y0
S1
1 − OF − 8
DECODER
14 Y1
15 Y2
12 Y3
1Y4
5Y5
2Y6
4Y7
3Z
10
S2
9
S3
6
87
VSS VEE
E
HEF4051B_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 11 September 2014 3 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
Fig 2. Schematic diagram (on e sw itc h)
001aac281
Yn
Z
VEE
VDD VDD
Fig 3. Logic symbol Fig 4. IEC logic symbol
001aac278
13 Y0
14
11 Y1S1
10
S2
9
S3
6
E
15 Y2
12 Y3
1Y4
5Y5
Z
3
2Y6
4Y7
3
1
MUX/DMUX 13
EN
14
15
12
31
5
2
4
0
1
2
3
4
5
6
7
001aac279
X0
7
11
10
9
6
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Product data sheet Rev. 2 — 11 September 2014 4 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
Fig 5. Logic diag ram
001aac280
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Z
LEVEL
CONVERTER
LEVEL
CONVERTER
S1
LEVEL
CONVERTER
S2
LEVEL
CONVERTER
S3
E
HEF4051B_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 11 September 2014 5 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 6. Pin configuration SOT109-1 Fig 7. Pin co nfiguration SOT403-1
+()%4
<
9''
<
<
=
<
<
<
<
<
(
6
9(
(
6
96
6
6
DDD
+()%4
< 9
''
< <
=<
<<
<<
(6
9
((
6
9
66
6
DDD
Table 2. Pin description
Symbol Pin Description
E6 enable input (active LOW)
VEE 7 supply voltage
VSS 8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4 independent input or output
Z 3 common output or input
VDD 16 supply voltage
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Product data sheet Rev. 2 — 11 September 2014 6 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
[1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional
switch must not exceed 0.4 V . If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there
is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
Table 3. Function table[1]
Input Channel ON
ES3 S2 S1
LLLLY0toZ
LLLHY1toZ
L L H L Y2toZ
L L H H Y3toZ
LHLLY4toZ
LHLHY5toZ
LHHLY6toZ
LHHHY7toZ
HXXXswitches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
VEE supply voltage referenced to VDD [1] 18 +0.5 V
IIK input clamping current pins Sn and E;
VI<0.5 V or VI>V
DD + 0.5 V -10 mA
VIinput voltage 0.5 VDD + 0.5 V
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO16 and TSSOP16
package [2] - 500 mW
P power dissipation per output - 100 mW
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Product data sheet Rev. 2 — 11 September 2014 7 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage see Figure 8 3- 15V
VIinput voltage 0 - VDD V
Tamb ambient temperature in fre e air 40 - +125 C
t/V input transition rise and fall
rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
Fig 8. Operating area as a function of the supply voltages
VDD − VEE (V)
015510
001aac285
10
5
15
VDD − VSS
(V)
0
operating area
Table 6. Static characteristics
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 CUnit
Min Max Min Max Min Max Min Max
VIH HIGH-level
input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level
input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
IIinput leakage
current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A
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Product data sheet Rev. 2 — 11 September 2014 8 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
10.1 Test circuits
IS(OFF) OFF-state
leakage
current
Z port;
all channels OFF;
see Figure 9
15 V - - - 1000 - - - - nA
Y port;
per channel;
see Figure 10
15 V - - - 200 - - - - nA
IDD supply current IO = 0 A 5 V - 5 - 5 - 150 - 150 A
10 V - 10 - 10 - 300 - 300 A
15 V - 20 - 20 - 600 - 600 A
CIinput
capacitance Sn, E inputs - - - - 7.5 - - - - pF
Table 6. Static characteristics …continued
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 CUnit
Min Max Min Max Min Max Min Max
Fig 9. Test circuit for measuring OFF-state leakage current Z port
I
S
001aak513
V
DD
VI
V
SS
= V
EE
S1 to S3
E
Z
V
DD
or V
SS
V
DD
Yn
VO
Fig 10. Test circuit for measuring OFF-state leakage current Yn port
I
S
001aak514
V
SS
VO
switch
V
SS
= V
EE
S1 to S3
E
Z
Y0
V
DD
or V
SS
V
DD
Yn
1
2
VI
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Product data sheet Rev. 2 — 11 September 2014 9 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
10.2 ON resistance
10.2.1 ON resistance waveform and test circuit
Table 7. ON resistance
Tamb = 25
C; ISW =200
A; VSS = VEE = 0 V.
Symbol Parameter Conditions VDD VEE Typ Max Unit
RON(peak) ON resistance (peak) VI = 0 V to VDD VEE;
see Figure 11 and Figure 12 5 V 350 2500
10 V 80 245
15 V 60 175
RON(rail) ON resistance (rail) VI = 0 V; see Figure 11 and Figure 12 5 V 115 340
10 V 50 160
15 V 40 115
VI = VDD VEE;
see Figure 11 and Figure 12 5 V 120 365
10 V 65 200
15 V 50 155
RON ON resistance mismatch
between channel s VI = 0 V to VDD VEE; see Figure 11 5 V 25 -
10 V 10 -
15 V 5 -
RON =V
SW /I
SW.
Fig 11. Test circuit for measuring RON
V
001aak512
V
SS
VI
VSW
ISW
V
SS
= V
EE
S1 to S3
E
Z
V
DD
or V
SS
V
DD
Yn
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Product data sheet Rev. 2 — 11 September 2014 10 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Fig 12. Typical RON as a function of input voltage
9,9
DDH
521
ȍ
9'' 9
9
9
Table 8. Dynamic characteristics
Tamb = 25
C; VSS = VEE = 0 V; for test circuit see Figure 16.
Symbol Parameter Conditions VDD Typ Max Unit
tPHL HIGH to LOW propagation delay Yn, Z to Z, Yn; see Figure 13 5 V 1530ns
10 V 5 10 ns
15 V 5 10 ns
Sn to Yn, Z; see Figure 14 5 V 150 300 ns
10 V 60 120 ns
15 V 4590ns
tPLH LOW to HIGH propagation delay Yn, Z to Z, Yn; see Figure 13 5 V 1530ns
10 V 5 10 ns
15 V 5 10 ns
Sn to Yn, Z; see Figure 14 5 V 150 300 ns
10 V 65 130 ns
15 V 4590ns
tPHZ HIGH to OFF-state
propagation delay Eto Yn, Z; see Figure 15 5 V 120 240 ns
10 V 90 180 ns
15 V 85 170 ns
tPZH OFF-state to HIGH
propagation delay Eto Yn, Z; see Figure 15 5 V 140 280 ns
10 V 55 110 ns
15 V 4080ns
tPLZ LOW to OFF-state
propagation delay Eto Yn, Z; see Figure 15 5 V 145 290 ns
10 V 120 240 ns
15 V 115 230 ns
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Product data sheet Rev. 2 — 11 September 2014 11 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
11.1 W aveforms and test circuit
tPZL OFF-stat e to LOW
propagation delay Eto Yn, Z; see Figure 15 5 V 140 280 ns
10 V 55 110 ns
15 V 4080ns
Table 8. Dynamic characteristics …continu ed
Tamb = 25
C; VSS = VEE = 0 V; for test circuit see Figure 16.
Symbol Parameter Conditions VDD Typ Max Unit
Measurement points are given in Table 9. Measurement points are given in Table 9.
Fig 13. Yn, Z to Z, Yn propagation delays Fig 14. Sn to Yn, Z propagation delays
001aak509
Yn or Z
input
Z or Yn
output
t
PLH
t
PHL
V
DD
V
EE
V
M
V
M
V
O
V
EE
001aak510
switch ON
t
PLH
t
PHL
switch OFF
V
DD
V
SS
V
O
V
EE
Yn or Z
output
Sn input
switch OFF
10 %
90 %
V
M
Measurement points are given in Table 9.
Fig 15. Enabl e and disable times
001aak511
tPLZ
tPHZ
switch OFF switch ONswitch ON
Yn or Z output
LOW-to-OFF
OFF-to-LOW
Yn or Z output
HIGH-to-OFF
OFF-to-HIGH
E input
VO
VO
VEE
VEE
VDD
VSS
VM
tPZL
tPZH
90 %
90 %
10 %
10 %
Table 9. Measurement points
Supply voltage Input Output
VDD VMVM
5 V to 15 V 0.5VDD 0.5VDD
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Product data sheet Rev. 2 — 11 September 2014 12 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
[1] For Yn to Z or Z to Yn propagation delays, use VEE. For Sn to Yn or Z propagation delays, use VDD.
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT= Termination resistance should be equal to output impedance Zo of the pulse generator.
CL= Load capacitance including test jig and probe.
RL= Load resistance.
Fig 16. Test circuit for measuring switching times
001aaj903
VIVO
RTCL
RLS1
DUT
PULSE
GENERATOR
tW
VM
VI
VI
VDD VDD
VSS
VEE
open
0 V
negative
pulse
VI
0 V
positive
pulse
10 %
90 %
90 %
10 % VM
VM
VM
tW
tftf
tr
tr
Table 10. Test data
Input Load S1 position
Yn, Z Sn and E tr, tfVMCLRLtPHL[1] tPLH tPZH, tPHZ tPZL, tPLZ other
VDD or VEE VDD or VSS 20 ns 0.5VDD 50 pF 10 kVDD or VEE VEE VEE VDD VEE
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Product data sheet Rev. 2 — 11 September 2014 13 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
11.2 Additional dynamic parameters
[1] fi is biased at 0.5 VDD; VI=0.5V
DD (p-p).
11.2.1 Test circuits
Table 11. Additional dynamic characteristics
VSS = VEE = 0 V; Tamb = 25
C.
Symbol Parameter Conditions VDD Typ Max Unit
THD total harmonic distortion see Figure 17; RL=10k; CL=15pF;
channel ON; VI=0.5V
DD (p-p);
fi=1kHz
5 V [1] 0.25 - %
10 V [1] 0.04 - %
15 V [1] 0.04 - %
f(3dB) 3 dB frequency response see Figure 18; RL = 1 k; CL = 5 pF;
channel ON; VI=0.5V
DD (p-p) 5 V [1] 13 - MHz
10 V [1] 40 - MHz
15 V [1] 70 - MHz
iso isolation (OFF-state) see Figure 19; fi= 1 MHz; RL = 1 k;
CL = 5 pF; channel OFF;
VI=0.5V
DD (p-p)
10 V [1] 50 - dB
Vct crosstalk voltage digital inputs to switch; see Figure 20;
RL = 10 k; CL=15pF;
Eor Sn = VDD (square-wave)
10 V 50 - mV
Xtalk crosstalk between switches; see Figure 21;
fi= 1 MHz; RL=1 k;
VI=0.5V
DD (p-p)
10 V [1] 50 - dB
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = VSS =0 V; t
r = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typi cal formula for PD (W) where:
PDdynamic power
dissipation 5V P
D = 1000 fi + (fo CL) VDD2fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
10 V PD = 5500 fi + (fo CL) VDD2
15 V PD = 15000 fi + (fo CL) VDD2
Fig 17. Test circuit for measuring total harmonic
distortion Fig 18. Test circuit for measuring frequency response
D
001aak516
V
SS
fi
RLCL
V
SS
= V
EE
S1 to S3
E
Z
V
DD
or V
SS
V
DD
Yn
dB
001aak517
V
SS
fi
RLCL
V
SS
= V
EE
S1 to S3
E
Z
V
DD
or V
SS
V
DD
Yn
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Product data sheet Rev. 2 — 11 September 2014 14 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
Fig 19. Test circuit for measuring isolation (OFF -state)
dB
001aak518
V
SS
fi
RLCL
switch
V
SS
= V
EE
S1 to S3
E
Z
Y0
V
DD
or V
SS
V
DD
Yn
1
2
a. Test circuit
b. Input and output pulse definitions
Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch
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92
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HEF4051B_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 11 September 2014 15 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
a. Switch closed condition b. Switch open condition
Fig 21. Test circuit for measuring crosstalk between switches
001aak520
V
SS VO
RLRL
V
SS
= V
EE
S1 to S3
E
Z
Y0
V
DD
or V
SS
V
DD
Yn
VI
001aak521
VSS VI
RL
RL
VSS = VEE
S1 to S3
E
Z
Y0
VDD or VSS
VDD
Yn
VO
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Product data sheet Rev. 2 — 11 September 2014 16 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
12. Package outline
Fig 22. Package outline SOT109-1 (SO16)
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HEF4051B_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 11 September 2014 17 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
Fig 23. Package outline SOT403-1 (TSSOP16)
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Product data sheet Rev. 2 — 11 September 2014 18 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
13. Abbreviations
14. Revision history
Table 13. Abbreviations
Acronym Description
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
MIL Military
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4051B_Q100 v.2 20140911 Product data sheet - HEF4051B_Q100 v.1
Modifications: •Figure 20: Test circuit modified
HEF4051B_Q100 v.1 20120712 Product data sheet - -
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Product data sheet Rev. 2 — 11 September 2014 19 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, t he product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe propert y or environment al
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
HEF4051B_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 11 September 2014 20 of 21
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2014
Document identifier: HEF4051B_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Recommended operating conditions. . . . . . . . 7
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
10.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 9
10.2.1 ON resistance waveform and test circuit . . . . . 9
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
11 .1 Waveforms and test circuit . . . . . . . . . . . . . . . 11
11.2 Additional dynamic parameters . . . . . . . . . . . 13
11.2.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16 Contact information. . . . . . . . . . . . . . . . . . . . . 20
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
