Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - (c) NXP N.V. (year). All rights reserved or (c) Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - (c) Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia HEF4051B-Q100 8-channel analog multiplexer/demultiplexer Rev. 2 -- 11 September 2014 Product data sheet 1. General description The HEF4051B-Q100 is an 8-channel analog multiplexer/demultiplexer with three address inputs (S1 to S3), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). The device contains eight bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y7) and the other side connected to a common input/output (Z). With E LOW, one of the eight switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. If break before make is needed, then it is necessary to use the enable input. VDD and VSS are the supply voltage connections for the digital control inputs (S1 to S3, and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (Y0 to Y7, and Z) can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics ESD protection: MIL-STD-833, method 3015 exceeds 2000V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4051BT-Q100 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4051BTT-Q100 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 5. Functional diagram VDD 16 13 Y0 S1 11 14 Y1 15 Y2 S2 10 12 Y3 LOGIC LEVEL CONVERSION 1 - OF - 8 DECODER 1 Y4 S3 9 5 Y5 2 Y6 4 Y7 E 6 3 Z 8 VSS Fig 1. 7 VEE 001aac277 Functional diagram HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 2 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer Yn VDD VDD Z VEE 001aac281 Fig 2. Schematic diagram (one switch) 11 10 9 13 S1 S2 S3 11 14 10 15 9 12 1 5 2 E 6 4 3 Y0 6 Y1 1 X 3 0 7 EN Y2 MUX/DMUX 0 Y3 Y4 1 Y5 2 Y6 3 3 4 Y7 5 Z 6 001aac278 7 13 14 15 12 1 5 2 4 001aac279 Fig 3. Logic symbol HEF4051B_Q100 Product data sheet Fig 4. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 3 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer Y0 Y1 S1 S2 S3 E LEVEL CONVERTER Y2 LEVEL CONVERTER Y3 LEVEL CONVERTER Y4 LEVEL CONVERTER Y5 Y6 Y7 Z 001aac280 Fig 5. Logic diagram HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 4 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning +()%4 < 9'' < < = < < < < < 9'' < < = < < < < < ( 6 9(( 6 966 < 6 9(( 6 966 ( +()%4 6 Fig 6. 6 DDD DDD Pin configuration SOT109-1 Fig 7. Pin configuration SOT403-1 6.2 Pin description Table 2. Pin description Symbol Pin Description E 6 enable input (active LOW) VEE 7 supply voltage VSS 8 ground supply voltage S1, S2, S3 11, 10, 9 select input Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4 independent input or output Z 3 common output or input VDD 16 supply voltage HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 5 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 7. Functional description 7.1 Function table Table 3. Function table[1] Input Channel ON E S3 S2 S1 L L L L Y0 to Z L L L H Y1 to Z L L H L Y2 to Z L L H H Y3 to Z L H L L Y4 to Z L H L H Y5 to Z L H H L Y6 to Z L H H H Y7 to Z H X X X switches off [1] H = HIGH voltage level; L = LOW voltage level; X = don't care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage Conditions [1] Min Max Unit 0.5 +18 V 18 +0.5 V - 10 mA VEE supply voltage referenced to VDD IIK input clamping current pins Sn and E; VI < 0.5 V or VI > VDD + 0.5 V VI input voltage 0.5 VDD + 0.5 V II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation - 500 mW - 100 mW Tamb = 40 C to +125 C SO16 and TSSOP16 package P [1] [2] power dissipation [2] per output To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 6 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage see Figure 8 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 001aac285 15 VDD - VSS (V) 10 operating area 5 0 0 Fig 8. 5 10 VDD - VEE (V) 15 Operating area as a function of the supply voltages 10. Static characteristics Table 6. Static characteristics VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current HEF4051B_Q100 Product data sheet Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit Conditions VDD Min Max Min Max Min Max Min Max IO < 1 A 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V IO < 1 A 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 15 V - 0.1 - 0.1 - 1.0 - 1.0 A All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 7 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer Table 6. Static characteristics ...continued VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IS(OFF) OFF-state leakage current Conditions CI Max Min Max Min Max Min Max Z port; 15 V all channels OFF; see Figure 9 - - - 1000 - - - - nA 15 V - - - 200 - - - - nA 5V - 5 - 5 - 150 - 150 A 10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A - - - - 7.5 - - - - pF supply current IO = 0 A input capacitance Tamb = 85 C Tamb = 125 C Unit Min Y port; per channel; see Figure 10 IDD Tamb = 40 C Tamb = 25 C VDD Sn, E inputs 10.1 Test circuits VDD S1 to S3 VDD or VSS Yn Z E IS VSS = VEE VDD VI VO 001aak513 Fig 9. Test circuit for measuring OFF-state leakage current Z port VDD VDD or VSS S1 to S3 Y0 1 Z Yn 2 switch IS E VSS = VEE VSS VO VI 001aak514 Fig 10. Test circuit for measuring OFF-state leakage current Yn port HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 8 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 10.2 ON resistance Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V. Symbol Parameter Conditions VDD VEE Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD VEE; see Figure 11 and Figure 12 5V 350 2500 10 V 80 245 15 V 60 175 5V 115 340 10 V 50 160 15 V 40 115 5V 120 365 10 V 65 200 15 V 50 155 RON(rail) ON resistance (rail) VI = 0 V; see Figure 11 and Figure 12 VI = VDD VEE; see Figure 11 and Figure 12 RON ON resistance mismatch between channels VI = 0 V to VDD VEE; see Figure 11 5V 25 - 10 V 10 - 15 V 5 - 10.2.1 ON resistance waveform and test circuit V VSW VDD VDD or VSS S1 to S3 Yn Z E VSS = VEE VSS ISW VI 001aak512 RON = VSW / ISW. Fig 11. Test circuit for measuring RON HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 9 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer DDH 521 9'' 9 9 9 9, 9 Fig 12. Typical RON as a function of input voltage 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16. Symbol Parameter tPHL HIGH to LOW propagation delay Yn, Z to Z, Yn; see Figure 13 Conditions Sn to Yn, Z; see Figure 14 tPLH LOW to HIGH propagation delay Yn, Z to Z, Yn; see Figure 13 Sn to Yn, Z; see Figure 14 tPHZ tPZH tPLZ HIGH to OFF-state propagation delay OFF-state to HIGH propagation delay LOW to OFF-state propagation delay HEF4051B_Q100 Product data sheet E to Yn, Z; see Figure 15 E to Yn, Z; see Figure 15 E to Yn, Z; see Figure 15 All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 VDD Typ Max Unit 5V 15 30 ns 10 V 5 10 ns 15 V 5 10 ns 5V 150 300 ns 10 V 60 120 ns 15 V 45 90 ns 5V 15 30 ns 10 V 5 10 ns 15 V 5 10 ns 5V 150 300 ns 10 V 65 130 ns 15 V 45 90 ns 5V 120 240 ns 10 V 90 180 ns 15 V 85 170 ns 5V 140 280 ns 10 V 55 110 ns 15 V 40 80 ns 5V 145 290 ns 10 V 120 240 ns 15 V 115 230 ns (c) NXP Semiconductors N.V. 2014. All rights reserved. 10 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer Table 8. Dynamic characteristics ...continued Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16. Symbol Parameter Conditions VDD Typ Max Unit tPZL OFF-state to LOW propagation delay E to Yn, Z; see Figure 15 5V 140 280 ns 10 V 55 110 ns 15 V 40 80 ns 11.1 Waveforms and test circuit VDD Yn or Z input VM VDD Sn input VEE tPLH tPLH VO Z or Yn output VM VSS tPHL tPHL VO 90 % Yn or Z output VM 10 % VEE VEE switch OFF switch ON 001aak509 switch OFF 001aak510 Measurement points are given in Table 9. Measurement points are given in Table 9. Fig 13. Yn, Z to Z, Yn propagation delays Fig 14. Sn to Yn, Z propagation delays VDD E input VM VSS tPLZ Yn or Z output LOW-to-OFF OFF-to-LOW tPZL VO 90 % 10 % VEE tPHZ VO tPZH 90 % Yn or Z output HIGH-to-OFF OFF-to-HIGH 10 % VEE switch ON switch OFF switch ON 001aak511 Measurement points are given in Table 9. Fig 15. Enable and disable times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 11 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer tW VI negative pulse 0V 90 % VM 10 % tf tr tr tf VI positive pulse 0V VM 10 % 90 % VM VM tW VDD VDD VI PULSE GENERATOR VI VO RL S1 open DUT RT CL VSS VEE 001aaj903 Test data is given in Table 10. Definitions: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including test jig and probe. RL = Load resistance. Fig 16. Test circuit for measuring switching times Table 10. Test data Input Yn, Z Load Sn and E tr, tf VDD or VEE VDD or VSS 20 ns [1] S1 position VM CL RL tPHL[1] 0.5VDD 50 pF 10 k VDD or VEE VEE tPLH tPZH, tPHZ tPZL, tPLZ other VEE VDD VEE For Yn to Z or Z to Yn propagation delays, use VEE. For Sn to Yn or Z propagation delays, use VDD. HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 12 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 11.2 Additional dynamic parameters Table 11. Additional dynamic characteristics VSS = VEE = 0 V; Tamb = 25 C. Symbol THD Parameter Conditions total harmonic distortion 3 dB frequency response f(3dB) VDD Typ Max Unit see Figure 17; RL = 10 k; CL = 15 pF; 5 V channel ON; VI = 0.5VDD (p-p); 10 V fi = 1 kHz 15 V [1] 0.25 - % [1] 0.04 - % [1] 0.04 - % see Figure 18; RL = 1 k; CL = 5 pF; channel ON; VI = 0.5VDD (p-p) 5V [1] 13 - MHz 10 V [1] 40 - MHz 70 - 50 15 V [1] iso isolation (OFF-state) see Figure 19; fi = 1 MHz; RL = 1 k; CL = 5 pF; channel OFF; VI = 0.5VDD (p-p) 10 V [1] Vct crosstalk voltage digital inputs to switch; see Figure 20; RL = 10 k; CL = 15 pF; E or Sn = VDD (square-wave) 10 V Xtalk crosstalk between switches; see Figure 21; fi = 1 MHz; RL = 1 k; VI = 0.5VDD (p-p) 10 V [1] 50 [1] MHz - dB - mV 50 - dB fi is biased at 0.5 VDD; VI = 0.5VDD (p-p). Table 12. Dynamic power dissipation PD PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter dynamic power dissipation PD VDD Typical formula for PD (W) 5V where: PD = 1000 fi + (fo CL) VDD 2 fi = input frequency in MHz; 10 V PD = 5500 fi + (fo CL) VDD 2 fo = output frequency in MHz; 15 V PD = 15000 fi + (fo CL) VDD2 CL = output load capacitance in pF; VDD = supply voltage in V; (CL fo) = sum of the outputs. 11.2.1 Test circuits VDD VDD or VSS VDD S1 to S3 VDD or VSS Yn Z S1 to S3 E VSS = VEE VSS RL CL D RL CL dB fi 001aak516 Fig 17. Test circuit for measuring total harmonic distortion Product data sheet VSS = VEE VSS fi HEF4051B_Q100 Yn Z E 001aak517 Fig 18. Test circuit for measuring frequency response All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 13 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer VDD VDD or VSS S1 to S3 Y0 1 Z Yn 2 switch E VSS = VEE VSS RL CL dB fi 001aak518 Fig 19. Test circuit for measuring isolation (OFF-state) 9'' 9'' 5/ 9'' 6WR6 < = <Q 5/ VZLWFK ( * 966 9(( 9''RU966 &/ 9 92 DDN a. Test circuit ORJLF LQSXW 6Q( RII RQ RII 92 9FW DDM b. Input and output pulse definitions Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 14 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer VDD VDD VDD or VSS S1 to S3 Y0 Z Yn VDD or VSS S1 to S3 Y0 Z Yn E E VSS = VEE VSS RL VO RL VSS = VEE VSS VI RL VI VO 001aak520 a. Switch closed condition RL 001aak521 b. Switch open condition Fig 21. Test circuit for measuring crosstalk between switches HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 15 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / H Z 0 ES GHWDLO; PP VFDOH ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP LQFKHV R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 22. Package outline SOT109-1 (SO16) HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 16 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ SLQLQGH[ $ $ $ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7( Fig 23. Package outline SOT403-1 (TSSOP16) HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 17 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Abbreviations Acronym Description HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model MIL Military 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4051B_Q100 v.2 20140911 Product data sheet - HEF4051B_Q100 v.1 - - Modifications: HEF4051B_Q100 v.1 HEF4051B_Q100 Product data sheet * Figure 20: Test circuit modified 20120712 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 18 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 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Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 19 of 21 HEF4051B-Q100 NXP Semiconductors 8-channel analog multiplexer/demultiplexer No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4051B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 11 September 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 20 of 21 NXP Semiconductors HEF4051B-Q100 8-channel analog multiplexer/demultiplexer 17. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 10.1 10.2 10.2.1 11 11.1 11.2 11.2.1 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ON resistance waveform and test circuit . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuit . . . . . . . . . . . . . . . 11 Additional dynamic parameters . . . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 September 2014 Document identifier: HEF4051B_Q100