74LCX74MX_NL - Fairchild Semiconductor

March 1995

Revised February 2005

74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs

74LCX74

Low Voltage Dual D-Type Positive

Edge- Triggere d F lip -Flop with 5 V To le ra nt Inputs

General Descript ion

The LCX74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Informati on at the inpu t is tr ansferr ed to th e outp uts on the

positive edge of the clock pulse. After the Clock Pulse input

threshold voltage has been passed, the Data input is

locked out and information present will not be transferred to

the outputs until the next rising edge of the Clock Pulse

input.

Asynchronous Inputs:

LOW input to SD (Set) sets Q to HIGH level

LOW input to CD (Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD makes both Q and

Q HIGH

Features

■5V tolerant inputs

■2.3V–3.6V VCC specifications provided

■7.0 ns tPD max (VCC

3.3V), 10

A ICC max

■Power down high impedance inputs and outputs

■

24 mA output drive (VCC

3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up performance exceeds JEDEC 78 conditions

■ESD performa nce :

Human body model

2000V

Machine model

200V

■Leadless Pb-Free DQFN package

Ordering Code:

Devices also available in Tape and Reel. Specify by append ing the suffix let t er “X” to th e ordering co de.

Pb-Free package per JEDEC J-STD-020B.

Note 1: DQFN packag e av ailable in Tape and Reel only.

Note 2: “_NL” indicates Pb-Fre e pac k age (per JE D EC J -STD-0 20B). Devic e availa ble in Tape and Reel only.

Order Number Package Package Description

Number

74LCX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX74MX_NL

(Note 2) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX74BQX

(Note 1) MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX74MTCX_NL

(Note 2) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

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74LCX74

Logic Symbols

IEEE/IEC

Pin Descriptions

Connection Diagrams

Pin Assignments for SOIC, SOP, and TSSOP

Pad Assignment for DQFN

(To p View)

Truth Table

(Each Half)

HIGH Voltage Lev el

LOW Voltage Level

Immaterial



LOW-to-HIGH Clock Transition

Q0(Q0)

Previo us Q(Q) before LOW-to-HIGH Transition of Clock

Pin Names Description

D1, D2Da ta I n p uts

CP1, CP2Clock Pulse Inputs

CD1, CD2 Direct Clear Inputs

SD1, SD2 Direct Set Inputs

Q1, Q1, Q2, Q2Outputs

Inputs Outputs

SDCDCP D Q Q

LHXXHL

HLXXLH

LLXXHH



HH L



LLH

HHLXQ

0Q0

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74LCX74

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions (Note 4)

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operat ed

at these limits. The para metric value s defined in the Elec trical Cha racteristic s tables are n ot guarantee d at the A bsolute Ma ximum R atings . The “Recom-

mended Operating Conditions” table will defin e th e c onditions f or ac t ual devic e operat ion.

Note 4: IO Absolu te Maximu m Rating must be observed.

Note 5: Unused input s m ust be he ld H I GH or LOW. They may not f loat.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



7.0 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Voltage



0.5 to VCC



0.5 Output in HIGH or LO W State (Note 4) V

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA



50 VO

VCC

IODC Output Source/Sink Current

50 mA

ICC DC Supply Current per Supply Pin

100 mA

IGND DC Ground Current per Ground Pin

100 mA

TSTG Storage Tempera ture



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 05.5V

VOOutput Voltage HIGH or LOW State 0 VCC V

IOH/IOL Output Curr en t VCC

3.0V



3.6V

24 mAVCC

2.7V



3.0V

VCC

2.3V



2.7V

TAFree-Air Operating Temperature



40 85

V Input Edge Rate, VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.3



2.7 1.7 V

2.7



3.6 2.0

VIL LOW Level Input Volt age 2.3



2.7 0.7 V

2.3



3.6 0.8

VOH HIGH Level Output Voltage IOH



100

A2.3



3.6 VCC - 0.2

IOH = -8 mA 2.3 1.8

IOH



12 mA 2.7 2.2

IOH



18 mA 3.0 2.4

IOH



24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL

100

A2.3



3.6 0.2

IOL = 8mA 2.3 0.6

IOL

12 mA 2.7 0.4 V

IOL

16 mA 3.0 0.4

IOL

24 mA 3.0 0.55

IIInput Leakage Current 0

5.5V 2.3



3.6

5.0

IOFF Power-Off Leakage Current VI or VO

5.5V 0 10

ICC Quiescent Supply Current VI

VCC or GND 2.3



3.6 10

3.6V

5.5V 2.3



3.6

ICC Increase in ICC per Input VIH

VCC



0.6V 2.3



3.6 500

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74LCX74

AC Electrical Characteristics

Note 6: Skew is de fi ned as th e absolut e valu e of the difference betwee n t he ac tu al propaga t ion delay f or any t w o separa t e outputs of t he same device. The

specif ic ation ap plies to an y o ut puts switch ing in the same direc t ion, either HIGH-to- LOW (tOSHL) or LO W-to-HIGH (t OSLH).

Dynamic Switching Characteristics

Capacitance

Symbol Parameter



C to



C, RL

500

Units

VCC

3.3V

0.3V VCC

2.7V VCC

2.5V

0.2V

50 pF CL

30 pF

Min Max Min Max Min Max

fMAX Maximum Clock Frequency 150 150 150 MHz

tPHL Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4 ns

tPLH CPn to Qn or Qn1.57.01.58.01.58.4

tPHL Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4 ns

tPLH CDn or SDn to Qn or Qn1.57.01.58.01.58.4

tSSetup Time 2.5 2.5 4.0 ns

tHHold Time 1.5 1.5 2.0 ns

tWPulse Width CP 3.3 3.3 4.0 ns

tWPulse Width and CD, SD3.3 3.6 4.0 ns

tREC Recovery Time 2.5 3.0 4.5 ns

tOSHL Output to Output Skew 1.0 ns

tOSLH (Note 6) 1.0

Symbol Parameter Conditions VCC

(V)

CUnit

Typical

VOLP Quiet Output Dynamic Peak VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3 0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5 0.6

VOLV Quiet Output Dynamic Peak VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3



0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5



0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC

Open, VI

0V or VCC 7pF

COUT Output Capacitance VCC

3.3V, VI

0V or VCC 8pF

CPD Power Dissipation Capacitance VCC

3.3V, VI

0V or VCC, f

10 MHz 25 pF

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74LCX74

AC Loading and Waveforms Generic for LCX Family

FIGURE 1. AC Test Circuit

(CL incl udes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay, Pulse Width and trec Waveforms

3-STATE Output High Enable and

Disable TImes for Logic

3-STATE Outp ut Low Enable and

Disable Times for Logic

Setup Time, Hold TIme and Recovery TIme for Logic

trise and tfall

FIGURE 2. Waveforms

(Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC

3.3

0.3V

VCC x 2 at VCC

2.5

0.2V

tPZH,tPHZ GND

Symbol VCC

3.3V

0.3V 2.7V 2.5V

0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL



0.3V VOL



0.3V VOL



0.15V

VyVOH



0.3V VOH



0.3V VOH



0.15V

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74LCX74

Schematic Diagram Generic for LCX Family

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74LCX74

Tape and Reel Specification

Tape Format for DQFN

TAPE DIMENSIONS inches (millimeters)

REEL DIMENSIONS inches (millimeters)

Packa ge Tape Number Cavit y Cove r Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

BQX Carrier 2500/3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Tape SizeABCDNW1W2

12 mm 13.0 0.059 0.512 0.795 7.008 0.488 0.724

(330) (1.50) (13.00) (20.20) (178) (12.4) (18.4)

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74LCX74

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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74LCX74

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

www.fairchildsemi.com 10

74LCX74

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm

Packag e Num b er MLP01 4A

11 www.fairchildsemi.com

74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC14

Fairchild does not assum e any responsibility for use of any circuitry des cribe d, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.