G2RL-1A4-E 12VDC - OMRON - Products.Network

 2013 Microchip Technology Inc. Advance Information DS25119C-page 1

Features

• Single Voltage Read and Write Operations

- 2.7-3.6V

• Serial Interface Architecture

- Nibble-wide multiplexed I/O’s with SPI-like serial

command structure

- Mode 0 and Mode 3

- x1/x2/x4 Serial Peripheral Interface (SPI) Proto-

col

• High Speed Clock Freque ncy

-104 MHz max

• Burst Modes

- Continuous linear burst

- 8/16/32/64 Byte linear burst with wrap-around

• Superior Reliability

- Endurance: 100,000 Cycles (min)

- Greater than 100 years Data Retention

• Low Power Consumption:

- Active Read current: 15 mA (typical @ 104 MHz)

- S t andby Current: 15 µA (typical)

• Page-Program

- 256 Bytes per page in x1 or x4 mode

• End-of-Write Detection

- Software polling the BUSY bit in status register

• Flexible Erase Capability

- Uniform 4 KByte sectors

- Four 8 KByte top and bottom parame ter overlay

blocks

- One 32 KByte top and bottom overlay block

- Uniform 64 KByte overlay blocks

• Write-Suspend

- Suspend Program or Erase opera tion to access

another block/sector

• Software Reset (RST) mode

• Software Write Protection

- Individual Block-Locking

- 64 KByte blocks, two 32 KByte blocks, and

eight 8 KByte parameter blocks

• Security ID

- One-T ime Programmable (OTP) 2 KByte,

Secure ID

- 64 bit unique, factory pre-programmed

identifier

- User-programmable area

• Temperature Range

- Industrial: -40°C to +85°C

• Packages Available

- 8-contact WSON (6mm x 5mm)

- 8-lead SOIC (200 mil)

- 16-lead SOIC (300 mil)

- 24-ball TBGA (6mm x 8mm)

• All devices are RoHS compliant

Product Description

The Serial Quad I/O™ (SQI™) family o f flash-memory

devices features a six-wire, 4-bit I/O interface that

allows for low-power, high -performance operation in a

low pin-count package. SST26VF064B/064BA also

support full command-set compatibility to traditional

Serial Peripheral Interface (SPI) protocol. System

designs using SQI flash devices occupy less board

space and ultimately lower system costs.

All members of the 26 Series, SQI family are manufac-

tured with proprietary , high-performance CMOS Super-

Flash® technology . The split-gate cell design and thick-

oxide tunneling injector attain better reliability and man-

ufacturability compared with alternate approaches.

The SST26VF064B/064BA significantly improve per-

formance and reliability, while lowering power con-

sumption. Th ese devices wri te (Program or Erase) with

a single power supply of 2.7-3.6V. The total energy

consumed is a functio n of the ap pli ed voltage, current,

and time of application. Since for any given voltage

range, the SuperFlash te chnol ogy us es less current to

program and has a shorter erase time, the total energy

consumed during any Erase or Program operation is

less than alternative flash memory technologies.

SST26VF064B/064BA are offered in 8-contact W SON

(6 mm x 5 mm), 8-lead SOIC (200 mil), 16-lead SOIC

(300 mil), and 24-ball TBGA. See Figure 2-2 for pin

assignments.

Two configurations are available upon order:

SST26VF064B default at power-up has the WP# and

Hold# pins enabled and SST26VF064BA default at

power-up has the WP# and Hold# pins disabled.

SST26VF064B / SST26VF064BA

3.0V Serial Quad I/O (SQI) Flash Memory

SST26VF064B / SST26VF064BA

DS25119C-page 2 Advance Information  2013 Microchip Technology Inc.

1.0 BLOCK DIAGRAM

FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM

25119 B1.0

Page Buffer,

I/O Buffers

and

Data Latches

SuperFlash

Memory

X - Decoder

Control Logic

Address

Buffers

and

Latches

HOLD#

Y - Decoder

CE# SIO [3:0]

Serial Interface

OTP

WP# SCK

 2013 Microchip Technology Inc. Advance Information DS25119C-page 3

SST26VF064B / SST26VF064BA

2.0 PIN DESCRIPTION

FIGURE 2-1: PIN DESCRIPTION FOR 8-LEAD SOIC

FIGURE 2-2: PIN DESCRIPTION FOR 8-CONTACT WSON

FIGURE 2-3: PIN DESCRIPTION FOR 16-LEAD SOIC

CE#

SO/SIO1

WP#/SIO2

VSS

VDD

HOLD/SIO3

SCK

SI/SIO0

Top View

25119 08-soic S2A P1.0

CE#

SO/SIO1

WP#/SIO2

VSS

Top View

VDD

HOLD/SIO3

SCK

SI/SIO0

25119 08-wson QA P1.0

SCK

SI/SIO0

VSS

WP#/SIO2

HOLD#/SIO3

VDD

CE#

SO/SIO116-SOIC P1.0

Top View

SST26VF064B / SST26VF064BA

DS25119C-page 4 Advance Information  2013 Microchip Technology Inc.

FIGURE 2-4: PIN DESCRIPTION FOR 24-BALL TBGA

TABLE 2-1: PIN DESCRIPTION

Symbol Pin Name Functions

SCK Serial Clock To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock

input, while output data is shifted out on the falling edge of the clock input.

SIO[3:0] Serial Data

Input/Output To transfer commands, addresses, or data serially into the device or data out of

the device. Inputs are latched on the rising edge of the serial clock. Data is

shifte d out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)

command instruction configures these pins for Qua d I/O mode.

SI Serial Data Input

for SPI mode To transfer commands, addresses or data serially into the device. Inputs are

latched on the rising edge of the serial clock. SI is the default state after a power

on reset.

SO Serial Data Output

for SPI mode To transfer data serially out of the device. Data is shifted out on the falling edge

of the serial clock. SO is the default state after a power on reset.

CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low

for the duration of any command sequence; or in the case of Write operations,

for the command/data input sequence.

WP# Write Protect The WP# is used in conjunction with the WPEN and IOC bits in the Configura-

tion register to prohibit write operations to the Block-Protection register . This pin

only works in SPI, single-bit and dual-bit Rea d mode.

HOLD# Hold Temporarily stops serial communication with the SPI Flash memory while the

device is selected. This pin only works in SPI, single-bit and dual-bit Read mode

and must be tied high when not in use.

VDD Power Supply To provide power supply voltage.

VSS Ground

SCK

VSS

VDD

CE#

WP#/

SIO2

S0/

SIO1

SI/

SIO0

HOLD#/

SIO3

ABCDEF

T4D-P1.0

Top View

 2013 Microchip Technology Inc. Advance Information DS25119C-page 5

SST26VF064B / SST26VF064BA

3.0 MEMORY ORGANIZATION

Th e SST26VF064B/064BA SQI mem ory array is o rga -

nized in uniform, 4 KByte erasable sectors with the fol-

lowing erasable blocks: eight 8 KByte parameter, two

32 KByte overlay, and 126 64 KByte overlay blocks.

See Figure 3-1.

FIGURE 3-1: MEMORY MAP

25119 F41.0

Top of Memory Block

8 KByte

32 KByte

64 KByte

32 KByte

8 KByte

Bottom of Memory Block

4 KByte

. . .

2 Sectors for 8 KByte blocks

8 Sectors for 32 KByte blocks

16 Sectors for 64 KByte blocks

. . .

SST26VF064B / SST26VF064BA

DS25119C-page 6 Advance Information  2013 Microchip Technology Inc.

4.0 DEVICE OPERATION

SST26VF064B/064BA support both Serial Peripheral

Interface (SPI) bus protocol and a 4-bit multiplexed SQI

bus protocol. To provide backward compatibility to tra-

ditional SPI Serial Flash devices, the device’s initial

state after a power-on reset is SPI mode which sup-

ports multi-I/O (x1/x2/x4) Read/Write commands. A

command instruction configures the device to SQI

mode. The dataflow in the SQI mode is similar to the

SPI mode, except it uses four multiplexed I/O signals

for command, address, and data sequence.

SQI Flash Memory supports both Mode 0 (0,0) and

Mode 3 (1,1) bus operations. The difference between

the two modes is the state of the SCK signal when the

bus master is in stand-by mode and no data is being

transferred. The SCK signal is low for Mode 0 and SCK

signal is high for Mode 3. For both modes, the Serial

Data I/O (SIO [3:0]) is sampled at the rising edge of the

SCK clock signal for input, and driven after the falling

edge of the SCK clock signal for output. The traditional

SPI protocol uses separate input (SI) and output (SO)

data signals as shown in Figure 4-1. The SQI protoc ol

uses four multiplexed signals, SIO[3:0], for both data in

and data out, as shown in Figure 4 -2. This means the

SQI protocol quadruples the traditional bus transfer

speed at the same clock frequency, without the need

for more pins on the package.

FIGURE 4-1: SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL

4.1 Device Protection

SST26VF064B/064BA offer a flexible memory protec-

tion scheme that allows the protection state of each

individual block to be controlled separately. In addition,

the Write-Protection Lock-Down register prevents any

change of the lock status during device operation. To

avoid inadvertent writes during power-up, the device is

write-protected by default after a power-on reset cycle.

A Global Block-Protection Unlock command offers a

single command cycle that unlocks the e ntire memory

array for faster manufacturing throughput.

For extra protection, there is an ad ditional non-volatile

Protection register bits for each individual block. Each

of the corresponding lock-down bits are one time pro-

grammable (OTP)—once written, they cannot be

erased. Data that had been previously programmed

into these blocks cannot be altered by programming or

erase and is not reversible

4.1.1 INDIVIDUAL BLOCK PROTECTION

SST26VF064B/064BA have a Block-Protection regis-

ter which provides a software mechanism to write-lock

the individual memory blocks and write-lock, and/or

read-lock, the individual parameter blocks. The Block-

Protection register is 144 bits wide: two bits each for the

eight 8 KByte parameter blocks (write-lock and read-

lock), and one bit each for the remaining 32 KByte and

64 KByte overlay blocks (write-lock). See Table 5-6 for

address range protected per register bit.

Each bit in the Block-Pro tection register (BPR) can be

written to a ‘1’ (protected) or ‘0’ (u nprotected). For the

parameter blocks, the most significant bit is for read-

lock, and the least significant bit is for write-lock. Read-

locking the parameter blocks provides additional secu-

rity for sensitive data after retrieval (e.g., after initial

boot). If a block is read-locked all reads to the block

return data 00H.

25119 F03.0

MODE 3

SCK

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB

25119 F04.0

MODE 3

CLK

SIO(3:0)

CE#

MODE 3

C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3

MODE 0MODE 0

MSB

 2013 Microchip Technology Inc. Advance Information DS25119C-page 7

SST26VF064B / SST26VF064BA

The Write Block-Protection Register command is a

two-cycle command which requires that Write-Enable

(WREN) is executed prior to the Write Block-Protection

Unlock command clears all write protection bits in the

Block-Protection register.

4.1.2 WRITE-PROTECTION LOCK-DOWN

(VOLATILE)

To prevent changes to the Block-Protection register,

use the Lock-Down Block-Protection Register (LBPR)

command to enable Write-Protection Lock-Down.

Once Write-Protection Lock-Down is enabled, the

Block-Protection register can not be changed. To avoid

inadvertent lock down, the WREN command must be

executed prior to the LBPR command.

To reset Write-Protection Lock-Down, performing a power

cycle on the device is required. The Write-Protection

Lock-Down status may be read from the St atus register.

4.1.3 WRITE-LOCK LOCK-DOWN (NON-

VOLATILE)

The non-Volatile Write-Lock Lock-Down register is an

alternate register that permanently prevents changes

to the block-protect bits. The non-Volatile Write-Lock

Lock-Down register (nVWLDR) is 136 bits wide per

device: one bit each for the eight 8-KByte parameter

blocks, and one bit each for the remaining 32 KByte

and 64 KByte overlay blocks. See Table 5-6 for address

range protected per register bit.

Writing ‘1’ to any or all of the nVWLDR bits disables the

change mechanism for the corresponding Write-Lock

bit in the BPR, and permanently sets this bit to a ‘1’

(protected) state. After this change, both bits will be set

to ‘1’, regardless of the data entered in subsequent

writes to either the nVWLDR or the BPR. Subsequent

writes to the nVWLDR can only alter available locations

that have not been previously written to a ‘1’. This

method provides write-protection for the corresponding

memory-array block by protecting it from future pro-

gram or erase operations.

Writing a ‘0’ in any location in the nVWLDR has no

effect on either the nVWLDR or the corresponding

Write-Lock bit in the BPR.

Note that if the Block-Protection register had been pre-

viously locked down, see “Write-Protection Lock-Down

(Volatile)”, the device must be power cycled before

using the nVWLDR. If the Block-Protection register is

locked down and the Write nVWLDR command is

accessed, the command will be ignored.

4.2 Hardware Write Protection

The hardware Write Protection pin (WP#) is used in

conjunction with the WPEN an d IOC bits in the co nfig-

uration register to prohibit write operations to the Block-

Protection and Configuration registers. The WP# pin

function only works in SPI single-bit and dual-bit read

mode when the IOC bit in the configuration register is

set to ‘0’.

The WP# pin function is disabled when the WPEN bit

in the configuration re gister is ‘0’. This allows installa-

tion of the SST26VF064B/064BA in a system with a

grounded WP# pin while still enabling Write to the

Block-Protection register. The Lock-Down function of

the Block-Protection Register supersedes the WP# pin,

see Table 4-1 for Write Protection Lock-Down states.

The factory default setting at power-up of the WPEN bit

is ‘0’, disabling the Write Protect function of the WP#

after power-up. WPEN is a non-volatile bit; once the bit

is set to ‘1’, the Write Protect function of the WP# pin

continues to be e nabled after power-up. The W P# pin

only protects the Block-Protection Register and Config-

uration Register from changes. Therefore, if the WP#

pin is set to low before or after a Program or Erase

command, or while an internal Write is in progress, it

will have no effect on the Write command.

The IOC bit takes priority over the WPEN bit in the con-

figuration register. When th e IOC bit is ‘1’, the fun ction

of the WP# pin is disabled and the WPEN bit serves no

function. When the IOC bit is ‘0’ and W PEN is ‘1’, set-

ting the WP# pin active low prohibi ts Write operations

to the Block Protection Register.

SST26VF064B / SST26VF064BA

DS25119C-page 8 Advance Information  2013 Microchip Technology Inc.

4.3 Security ID

SST26VF064B/064BA offer a 2 KByte Security ID (Sec

ID) feature. The Security ID space is divided into two

parts – one factory-programmed, 64-bit segment and

one user-programmable segment. The factory-pro-

grammed segment is programmed during manufactur-

ing with a unique number and cannot be changed. The

user-programmable segment is left unprogrammed for

the customer to program as desi red.

Use the Program Security ID (PSID) co mmand to pro-

gram the Security ID using the address shown in Table

5-5. The Security ID can be locked using the Lockout

Security ID (LSID) command. This prevents any future

write operations to the Security ID.

The factory-programmed portion of the Security ID

can’t be programmed by the user; neither the factory-

programmed nor user-programmable areas can be

erased.

4.4 Hold Operation

The HOLD# pin pauses active serial sequences with-

out resetting the clocking sequence. This pin is ac tive

after every power up and only operates during SPI

single-bit and dual-bit modes. T wo factory configura-

tions are available: SST26VF0 64B ships with the IOC

bit set to ‘0’ and the HOLD# pin function enabled;

SST26VF064BA ships with the IOC bit set to ‘1’ and the

HOLD# pin function disabled. The HOLD# pin is always

disabled in SQI mode and only works in SPI single-bit

and dual-bit read mode.

To activate the Hold mode, CE# must be in active low

state. The Hold mode begins when the SCK active low

state coincides with the falling edge of the HOLD# sig-

nal. The Hold mode ends when the HOLD# signal’s ris-

ing edge coincides with the SCK active low state.

If the falling edge of the HOLD# signal does not coin-

cide with the SCK active low state, then the device

enters Hold mode when the SCK next reaches the

active low state. Similarly, if the rising edge of the

HOLD# signal does not coincide with the SCK active

low state, then the device exits Hold mode when the

SCK next reaches the active low state. See Figure 4-3.

Once the device enters Hold mod e, SO will be in high

impedance state while SI and SCK can be VIL or VIH.

If CE# is driven active high during a Hold condition, it

resets the internal logic of the device. As long as

HOLD# signal is low, the memory remains in the Hold

condition. To resume communication with the device,

HOLD# must be driven active high, and CE# must be

driven active low.

FIGURE 4-3: HOLD CONDITION WAVEFORM.

TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES

WP# IOC WPEN WPLD Execute WBPR Instruction Configuration Register

L0 1 1Not Allowed Protected

L0 0 1Not Allowed Writable

L0 1 0Not Allowed Protected

1020Allowed Writable

H0 X 1Not Allowed Writable

H0 X 0Allowed Writable

X1 X 1Not Allowed Writable

3020Allowed Writable

1. Default at power-up Register settings for SST26VF064B

2. Factory default setting is ‘0’. This is a non-volatile bit; default at power-up is the value set prior to power-down.

3. Default at power-up Register settings for SST26VF064BA

Active Hold Active Hold Active

25119 F46.0

SCK

HOLD#

 2013 Microchip Technology Inc. Advance Information DS25119C-page 9

SST26VF064B / SST26VF064BA

4.5 Status Register

The S tatus register is a read-only register that provides

the following status information: whether the flash

memory array is available for any Read or Write oper-

ation, if the device is write-enabled, whether an e rase

or program operation is suspended, and if the Block-

Protection register and/or Security ID are locked down.

During an internal Erase or Program operation, the S ta-

tus register may be read to determine the completion of

an operation in progress. Table 4-2 describes the func-

tion of each bit in the Status register.

TABLE 4-2: STATUS REGISTER

Bit Name Function Default at

Power-up Read/Write (R/

0BUSY Write ope ration status

1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

1WEL Write-Enable Latch status

1 = Device is write-enabled

0 = Device is not write-enabled

2WSE Write Suspend-Erase statu s

1 = Erase suspen de d

0 = Erase is not suspen d ed

3WSP Write Suspend-Program statu s

1 = Program suspended

0 = Program is not suspended

4WPLD Write Protection Lock-Down status

1 = Write Protection Lock-Down enabled

0 = Write Protection Lock-Down disabled

5SEC1

1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security ID instruction, oth-

erwise default at power-up is ‘0’.

Security ID status

1 = Security ID space locked

0 = Security ID space not locked

01R

6RES Reserved for future use 0R

7BUSY Write ope ration status

1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

SST26VF064B / SST26VF064BA

DS25119C-page 10 Advance Information  2013 Microchip Technology Inc.

4.5.1 WRITE-ENABLE LATCH (WEL)

The Write-Enable Latch (WEL) bit indicates the status

of the internal memory’s Write-Enable Latch. If the

WEL bit is set to ‘1’, the device is write enabled. If the

bit is set to ‘0’ (reset), the device is not write enabled

and does not accept any memory Program or Erase,

Protection Register Write, or Lock-Down commands.

The Write-Enable Latch bit is automatically reset under

the following conditions:

• Power-up

• Reset

• Write-Disable (WRDI) instruction completion

• Page-Program instruction completion

• Sector-Erase instruction completion

• Block-Erase instruction completion

• Chip-Erase instruction comple tion

• Write-Block-Protection register instruction

• Lock-Down Block-Protection register instruction

• Program Security ID instruction completion

• Lockout Security ID instruction completion

• Write-Suspend instruction

• SPI Quad Page program instruction completion

• Write Status Registe r

4.5.2 WRITE SUSPEND ERASE STATUS

(WSE)

The Write Suspend-Erase status (WSE) indicates

when an Erase operation has been suspended. The

WSE bit is ‘1’ after the host issues a suspend command

during an Erase operation. Once the suspended Erase

resumes, the WSE bit is reset to ‘0’.

4.5.3 WRITE SUSPEND PROGRAM

STATUS (WSP)

The Write Suspend-Program status (WSP) bit indicates

when a Program operati on has been suspended. The

WSP is ‘1’ after the host issues a suspend command

during the Program operation. Once the suspended

Program resumes, the WSP bit is reset to ‘0’.

4.5.4 WRITE PROTECTION LOCK-DOWN

STATUS (WPLD)

The Write Protection Lock-Down status (WPLD) bit

indicates when the Block-Protection re gister is l ocked-

down to prevent changes to the protection settings.

The WPLD is ‘1’ after the host issues a Lock-Down

Block-Protection command. After a power cycle, the

WPLD bit is reset to ‘0’.

4.5.5 SECURITY ID STATUS (SEC)

The Security ID Status (SEC) bit indicates when the

Security ID space is locked to prevent a Write com-

mand. The SEC is ‘1’ after the host issues a Lockout

SID command. Once the host issues a Lockout SID

command, the SEC bit can never be reset to ‘0.’

4.5.6 BUSY

The Busy bit determines whether there is an internal

Erase or Program operation in progress. If the BUSY

bit is ‘1’, the device is busy with an internal Erase or

Program operation. If the bit is ‘0’, no Erase or Program

operation is in progress.

4.5.7 CONFIGURATION REGISTER

The Configuration register is a Read/Write register that

stores a variety of configuration information. See Table

4-3 for the function of each bit in the register.

TABLE 4-3: CONFIGURATION REGISTER

Bit Name Function D e f a u l t a t Pow e r- u p Read/Write (R/W)

0RES Reserved 0R

1IOC I/O Configuration for SPI Mode

1 = WP# and HOLD# pins disabled

0 = WP# and HOLD# pins enabled

1. SST26VF064B default at Power-up is ‘0’

SST26VF064BA default at Power-up is ‘1’

R/W

2RES Reserved 0R

3BPNV Bl ock-Pro tection Volatility State

1 = No memory block has been permanently locked

0 = Any block has been permanently locked

4RES Reserved 0R

5RES Reserved 0R

6RES Reserved 0R

7WPEN Write-Protection Pin (WP#) Enable

1 = WP# enabled

0 = WP# disabled

2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.

R/W

 2013 Microchip Technology Inc. Advance Information DS25119C-page 11

SST26VF064B / SST26VF064BA

4.5.8 I/O CONFIGURATION (IOC)

The I/O Configuration (IOC) bit re-configures the I/O

pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the

Configuration register. When IOC bit is ‘0’ the WP# pin

and HOLD# pin are enabled (SPI or Dual Configuration

setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3

pin are enabled (SPI Quad I/O Configuration setup).

The IOC bit must be set to ‘1’ before issuing the follow-

ing SPI commands: SQOR (6BH), SQIOR (EBH),

RBSPI (ECH), and SPI Quad page program (32H).

Without setting the IOC bit to ‘1’, those SPI commands

are not valid. The I/O configuration bit does not apply

when in SQI mode. The default at power-up for

SST26VF064B is ‘0’ and for SST26VF064BA is ‘1’.

4.5.9 BLOCK-PROTECTION VOLATILITY

STATE (BPNV)

The Block-Protection Volatility State bit indicates

whether any block has been permanently locked with

the nVWLDR. When no bits in the nVWLDR have been

set, the BPNV is ‘1’; this is the default state from the

factory. When one or more bits in the nVWLDR are set

to ‘1’, the BPNV bit will also be ‘0’ from that point for-

ward, even after power-up.

4.5.10 WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a non-vola tile

bit that enables the WP# pin.

The Write-Protect (WP#) pin and the Write-Protect

Enable (WPEN) bit control the programmable hard-

ware write-protect feature. Setting the WP# pin to low,

and the WPEN bit to ‘1’, enables Hardware write-pro-

tection. To disable Hardware write protection, set either

the WP# pin to high or the WPEN bit to ‘0’. There is

latency associated with writing to the WPEN bit. Poll

the BUSY bit in the Status register, or wait TWPEN, for

the completion of the internal, self-timed Write opera-

tion. When the chip is hardware write protected, only

Write operations to Block-Protection and Configuration

registers are disabled. See “Hardware Write Protec-

tion” on page 7 and Table 4-1 on page 8 for more infor-

mation about the functionality of the WPEN bit.

SST26VF064B / SST26VF064BA

DS25119C-page 12 Advance Information  2013 Microchip Technology Inc.

5.0 INSTRUCTIONS

Instructions are used to read, write (erase and pro-

gram), and configure the SST26VF064B/064BA. The

complete list of the instructions is provided in T able 5-1.

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

Instruction Description Command

Cycle1Mode Address

Cycle(s)2, 3 Dummy

Cycle(s)3Data

Cycle(s)3Max

FreqSPI SQI

Configuration

NOP No Operation 00H X X 0 0 0 104

MHz

RSTEN Reset Enable 66H X X 0 0 0

RST4Reset Memory 99H X X 0 0 0

EQIO Enable Quad I/O 38HX 0 0 0

RSTQIO5Reset Quad I/O FFH X X 0 0 0

RDSR Read Status Register 05H X 0 0 1 to ∞

X0 11 to ∞

WRSR Writ e Status Register 01H X X 0 0 2

RDCR Read Configuration

X0 11 to ∞

Read

Read Read Memory 03H X 3 0 1 to ∞40

MHz

High-Speed

Read Read Memory at Higher

Speed 0BH X 3 3 1 to ∞104

MHz

X311 to ∞

SQOR6SPI Quad Output Read 6BH X 3 1 1 to ∞

SQIOR7SPI Quad I/O Read EBH X 3 3 1 to ∞

SDOR8SPI Dual Output Read 3BH X 3 1 1 to ∞

SDIOR9SPI Dual I/O Read BBH X 3 1 1 to ∞80 MHz

SB Set Burst Length C0H X X 0 0 1 104

MHz

RBSQI SQI Read Burst with Wrap 0CH X 3 3 n to ∞

RBSPI7SPI Read Burst with Wrap ECH X 3 3 n to ∞

Identification

JEDEC-ID JEDEC-ID Read 9FH X 0 0 3 to ∞104

MHz

Quad J-ID Quad I/O J-ID Read AFH X 0 1 3 to ∞

SFDP Serial Flash Discoverable

Parameters 5AH X 3 1 1 to ∞

Write

WREN Write Enable 06H X X 0 0 0 104

MHz

WRDI Writ e Disable 04H X X 0 0 0

SE10 Erase 4 KBytes of Memory

Array 20H X X 3 0 0

BE11 Erase 64, 32 or 8 KBytes of

Memory Array D8HXX 3 0 0

CE Erase Full Array C7H X X 0 0 0

PP Page Program 02H X X 3 0 1 to 256

SPI Quad

PP6SQI Quad Page

Program 32H X 3 0 1 to 256

 2013 Microchip Technology Inc. Advance Information DS25119C-page 13

SST26VF064B / SST26VF064BA

WRSU Suspends Program/Erase B0H X X 0 0 0 104

MHz

WRRE Resumes Program/Erase 30H X X 0 0 0

Protection

RBPR Read Blo ck-Pr otection

MHz

X0 11 to 18

WBPR Write Block -Protection

LBPR Lock Down

Block-Protection

8DH X X 0 0 0

nVWLDR non-Volatile Write Lock-

Down Register E8H X X 0 0 1 to 18

ULBPR Global Block Protection

Unlock 98HXX 0 0 0

RSID Read Security ID 88H X 2 1 1 to 2048

X 2 3 1 to 2048

PSID Program User

Security ID area A5H X X 2 0 1 to 256

LSID Lockout Security ID Pro-

gramming 85H X X 0 0 0

1. Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.

2. Address bits above the most significant bit of each density can be VIL or VIH.

3. Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode.

4. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.

5. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.

6. Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.

7. Address , Dummy/Mo de bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ bef ore issuing the command.

8. Data cycles are four clock periods.

9. Address, Dummy/Mode bits, and Data cycles are four clock per iods.

10. Sector Addresses: Use AMS - A12, remaining address are don’t care, but must be set to VIL or VIH.

11. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: AMS - A16 for 64 KByte; AMS - A15

for 32 KByte; AMS - A13 for 8 KByte. Remaining addresses are don’t care, but must be set to VIL or VIH.

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

Instruction Description Command

Cycle1Mode Address

Cycle(s)2, 3 Dummy

Cycle(s)3Data

Cycle(s)3Max

FreqSPI SQI

SST26VF064B / SST26VF064BA

DS25119C-page 14 Advance Information  2013 Microchip Technology Inc.

5.1 No Operation (NOP)

The No Operation command only cancels a Reset

Enable command. NOP has no impact on any other

command.

5.2 Reset-Enable (RSTEN) and Reset

(RST)

The Reset operation is used as a system (software)

reset that puts the device in normal operating Ready

mode. This operation consists of two commands:

Reset-Enable (RSTEN) followed by Reset (RST).

To reset the SST26VF064B/064BA, the host drives

CE# low, sends the Reset-Enable command (66H),

and drives CE# high. Next, the host drives CE# low

again, sends the Reset command (99H), and drives

CE# high, see Figure 5-1.

The Reset operation requires the Reset-Enable com-

mand followed by the Reset co mmand. Any co mmand

other than the Reset command after the Reset-Enable

command will disable the Reset-Enable.

Once the Reset-Enable and Reset commands are suc-

cessfully executed, the device returns to normal opera-

tion Read mode and then does the following: resets the

protocol to SPI mode, resets the burst length to 8

Bytes, clears all the bits, except for bit 4 (WPLD) and

bit 5 (SEC), in the St atus register to their default states,

and clears bit 1 (IOC) in the configuration register to its

default state. A device reset during an active Program

or Erase operation aborts the operation, which can

cause the data of the t argeted address range to be cor-

rupted or lost. Depending on the prior operation, the

reset timing may vary . Recovery from a Write operation

requires more latency time than recovery from other

operations. See Table 8-2 on page 48 for Rest timing

parameters.

FIGURE 5-1: RESET SEQUENCE

5.3 Read (40 MHz)

The Read instruction, 03H, is supported in SPI bus pro-

tocol only with clock frequencies up to 40 MHz. This

command is not supported in SQI bus protocol. The

device outputs the data starting from the specified

address location, then continuously streams the data

output through all addresses until terminated by a low-

to-high transition on CE#. The internal address pointer

will automatically increment until the highest memory

address is reached. Once the highest memory address

is reached, the address pointer will automatically return

to the beginning (wrap-arou nd) of the address space.

Initiate the Read instruction by executing an 8-bit com-

mand, 03H, followed by address bits A[23:0]. CE# must

remain active low for the duration of the Read cycle.

See Figure 5-2 for Read Sequence.

FIGURE 5-2: READ SEQUENCE (SPI)

25119 F05.0

MODE 3

CLK

SIO(3:0)

CE#

MODE 3

C1 C3 C2C0

MODE 0

MODE 3

MODE 0MODE 0

TCPH

Note: C[1:0] = 66H; C[3:2] = 99H

25119 F29.0

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 7047 48 55 56 63 64

N+2 N+3 N+4N N+1

OUT

MSB MSB

MSB

MODE 0

MODE 3

OUT

 2013 Microchip Technology Inc. Advance Information DS25119C-page 15

SST26VF064B / SST26VF064BA

5.4 Enable Quad I/O (EQIO)

The Enable Quad I/O (EQIO) instruction, 38H, enables

the flash device for SQI bus operation. Upon comple-

tion of the instruction, all instructions thereafter are

expected to be 4-bit multiplexed input/output (SQI

mode) until a power cycle or a “Reset Quad I/O instruc-

tion” is executed. See Figure 5-3.

FIGURE 5-3: ENABLE QUAD I/O SEQUENCE

5.5 Reset Quad I/O (RSTQIO)

The Reset Quad I/O instruction, FFH, resets the device

to 1-bit SPI protocol operation or exits the Set Mode

configuration during a read sequence. This command

allows the flash device to return to the default I/O state

(SPI) without a power cycle, and executes in either 1-

bit or 4-bit mode. If the device is in the Set Mode con-

figuration, while in SQI High-Speed Read mode, the

RSTQIO command will only return the device to a state

where it can accept new command instruction. An addi-

tional RSTQIO is required to reset the device to SPI

mode.

To execute a Reset Quad I/O operation, the host drives

CE# low, sends the Reset Quad I/O command cycle

(FFH) then, drives CE# high. Execute the instruction in

either SPI (8 clocks) or SQI (2 clocks) command

cycles. For SPI, SIO[3:1] are don’t care for this com-

mand, but should be driven to VIH or VIL. See Figures

5-4 and 5-5.

FIGURE 5-4: RESET QUAD I/O SEQUENCE (SPI)

FIGURE 5-5: RESET QUAD I/O SEQUENCE (SQI)

25119 F43.0

MODE 3 0 1

SCK

SIO0

CE#

MODE 0

234567

SIO[3:1]

Note: SIO[3:1] must be driven VIH

25119 F73.0

MODE 3 0 1

SCK

SIO0

CE#

MODE 0

234567

SIO[3:1]

Note: SIO[3:1] must be driven VIH

25119 F74.0

MODE 3 0 1

SCK

SIO(3:0)

CE#

MODE 0

SST26VF064B / SST26VF064BA

DS25119C-page 16 Advance Information  2013 Microchip Technology Inc.

5.6 High-Speed Read (104 MHz)

The High-S peed Read instruction, 0BH, is supported in

both SPI bus protocol and SQI protocol. On power-up,

the device is set to use SPI.

Initiate High-Speed Read by executing an 8-bit com-

mand, 0BH, followed by address bits A[23-0] and a

dummy byte. CE# must remain active low for the dura-

tion of the High-Speed Read cycle. See Figure 5-6 for

the High-Speed Read sequence for SPI bus protocol.

FIGURE 5-6: HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)

In SQI protocol, the host drives CE# low then send the

Read command cycle command, 0BH, followed by

three address cycles, a Set Mode Configuration cycle,

and two dummy cycles. Each cycle is two nibbles

(clocks) long, most significant nibble first.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the speci-

fied address location. The device continually streams

data output through all addresses until terminated by a

low-to-high transition on CE#. The internal address

pointer automatically increments until the highest mem-

ory address is reached, at which point the address

pointer returns to address location 000000H. During

this operation, blocks that are Read-locked will output

data 00H.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SQI High-S peed Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another Read com-

mand, 0BH, and does not require the op-code to be

entered again. The host may initiate the next Read

cycle by driving CE# low, then sending the four-bits

input for address A[23:0], followed by the Set Mode

configuration bits M[7:0], and two dummy cycles. After

the two dummy cycles, the device outputs the data

starting from the specified address location. There are

no restrictions on address location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. While in

the Set Mode configuration, the RSTQIO command will

only return the device to a state where it can accept

new command instruction. An additional RSTQIO is

required to reset the device to SPI mode. See Figure 5-

10 for the SPI Quad I/O Mode Read sequence when

M[7:0] = AXH.

FIGURE 5-7: HIGH-SPEED READ SEQUENCE (SQI)

25119 F31.0

CE#

SO/SIO1

SI/SIO0

SCK

ADD.

012345678

ADD. ADD.0B

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63 64

N+2 N+3 N+4

NN+1

MSB

MODE 0

MODE 3

OUT

71 72

OUT

Address Dummy

CommandCommand Data Byte 0

MSN LSN

Data Byte 7

Mode

25119 F47.0

012

SCK

SIO(3:0)

CE#

C1C0 A5 A4 A3 A2 A1 A0 XH0XXX L0 H8 L8

78 111091312 1514 2120

MODE 3

MODE 0

3456

M1 M0

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

Hx = High Data Nibble, Lx = Low Data Nibble C[1:0]=0BH

 2013 Microchip Technology Inc. Advance Information DS25119C-page 17

SST26VF064B / SST26VF064BA

5.7 SPI Quad-Output Read

The SPI Quad-Output Read in struction supports up to

104 MHz frequency. SST26VF064B requires the IOC

bit in the configuration register to be set to ‘1’ prior to

executing the command. Initiate SPI Quad-Output

Read by executing an 8-bit command, 6BH, followed

by address bits A[23-0] and a dummy byte. CE# must

remain active low for the duration of the SPI Quad

Mode Read. See Figure 5-8 for the SPI Quad Output

Read sequence.

Following the dummy byte, the device outputs data

from SIO[3:0] starting from the specified address loca-

tion. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal address pointer auto-

matically increments until the highest memory address

is reached, at which point the address pointer returns

to the beginning of the address space.

FIGURE 5-8: SPI QUAD OUTPUT READ

CE#

SIO0

SCK 012345678 31 32

MODE 3

MODE 0 15 16 23

6BH

25119 F48.3

39 40 41

A[23:16] A[15:8] A[7:0]

b4 b0 b4 b0

b5 b1 b5 b1

b6 b2 b6 b2

b7 b3 b7 b3

SIO1

SIO2

SIO3

Address

OP Code Data

Byte 0

Dummy Data

Byte N

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

SST26VF064B / SST26VF064BA

DS25119C-page 18 Advance Information  2013 Microchip Technology Inc.

5.8 SPI Quad I/O Read

The SPI Quad I/O Read (SQIOR) instruction supports

up to 104 MHz frequency. SST26VF064B requires the

IOC bit in the configuration register to be set to ‘1’ prior

to executing the command. Initiate SQIOR by execut-

ing an 8-bit command, EBH. The device then switches

to 4-bit I/O mode for address bits A[23-0], followed by

the Set Mode configuration bits M[7:0], and two dummy

bytes.CE# must remain active low for the duration of

the SPI Quad I/O Read. See Figure 5-9 for the SPI

Quad I/O Read sequence.

Following the dummy bytes, the device outputs data

from the specified address location. The device contin-

ually streams data output through all addresses until

terminated by a low-to-high transition on CE#. The

internal address pointer auto matically increments until

the highest memory address is reached, at which point

the address pointer returns to the beginning of the

address space.

The Set Mode Configuration bit M[7:0] in dicates if the

next instruction cycle is another SPI Quad I/O Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another Read com-

mand, EBH, and does not require the op-code to be

entered again. The host may set the next SQIOR cycle

by driving CE# low , then sending the four-bit wide input

for address A[23:0], followed by the Set Mode configu-

ration bits M[7:0], and two dummy cycles. Af ter the two

dummy cycles, the device outputs the data starting

from the specified address location. There are no

restrictions on address location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Rese t Qua d I/O command, F FH. Se e Fig-

ure 5-10 for the SPI Quad I/O Mode Read sequence

when M[7:0] = AXH.

FIGURE 5-9: SPI QUAD I/O READ SEQUENCE

A20 A16A12

A8 A4 A0 M4 M0

CE#

SIO0

SCK 012345678 16 17

MODE 3

MODE 0 91011

EBH

25119 F49.2

b4 b0

SIO1

SIO2

SIO3

Address Data

Byte 0

Dummy

1513 14 23

1918 2220 21

b4 b0

A21 A17A13

A9 A5 A1 M5 M1 b5 b1 b5 b1

A22 A18A14

A10 A6 A2 M6 M2 b6 b2 b6 b2

A23 A19A15

A11 A7 A3 M7 M3 b7 b3 b7 b3

Set

Mode Data

Byte 1

MSN LSN

XXXX

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

 2013 Microchip Technology Inc. Advance Information DS25119C-page 19

SST26VF064B / SST26VF064BA

FIGURE 5-10: BACK-TO-BACK SPI QUA D I/O READ SEQUENCES WHEN M[7:0] = AXH

5.9 Set Burst

The Set Burst command specifies the number of bytes

to be output during a Read Bu rst command before th e

device wraps around. It supports both SPI and SQI pro-

tocols. To set the burst length the host drives CE# low,

sends the Set Burst command cycle (C0H) and one

data cycle, then drives CE# high. After power-up or

reset, the burst length is set to eig ht Bytes (00H). See

Table 5-2 for burst length data and Figures 5-11 and 5-

12 for the sequences.

FIGURE 5-11: SET BURST LENGTH SEQUENCE (SQI)

A20A16 A12 A8 A4 A0 M4 M0

CE#

SIO0

SCK 01 910

5234

25119 F50.2

b4 b0

SIO1

SIO2

SIO3

Address Data

Byte 0

Dummy

867 1211 13

b4 b0

Set

Mode

MSN LSN

b4 b0

XXXX

A21A17 A13 A9 A5 A1 M5 M1

b5 b1 b5 b1 b5 b1

XXXX

A22A18 A14 A10 A6 A2 M6 M2

b6 b2 b6 b2 b6 b2

XXXX

A23A19 A15 A11 A7 A3 M7 M3

b7 b3 b7 b3 b7 b3

XXXX

Data

Byte

Data

Byte

N+1

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

TABLE 5-2: BURST LENGTH DATA

Burst Length High Nibble (H0) Low Nibble (L0)

8 Bytes 0h 0h

16 Bytes 0h 1h

32 Bytes 0h 2h

64 Bytes 0h 3h

25119 F32.0

MODE 3 0 1

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

H0 L0

MSN LSN

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0]=C0H

SST26VF064B / SST26VF064BA

DS25119C-page 20 Advance Information  2013 Microchip Technology Inc.

FIGURE 5-12: SET BURST LENGTH SEQUENCE (SPI)

5.10 SQI Read Burst with Wrap (RBSQI)

SQI Read Burst with wrap is similar to High Speed

Read in SQI mode, except data will output continuously

within the burst length until a low-to-high transition on

CE#. To execute a SQI Read Burst operation, drive

CE# low then send the Read Burst command cycle

(0CH), followed by three address cycles, and then

three dummy cycles. Each cycle is two nibbles (clocks)

long, most significant nibble first.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the speci-

fied address location. The data output stream is contin-

uous through all addresses until terminated by a low-to-

high transition on CE#.

During RBSQI, the internal address pointer automati-

cally increments until the last byte of the burst is

reached, then it wraps around to the first byte of the

burst. All bursts are aligned to addresses within the

burst length, see Table 5-3. For example, if the burst

length is eight Bytes, an d the start address is 06h, the

burst sequence would be: 06h, 07h, 00h, 01h, 02h,

03h, 04h, 05h, 06h, etc. The pattern repeats until the

command is terminated by a low-to-high transition on

CE#.

During this operation, blocks that are Read-l ocked will

output data 00H.

5.11 SPI Read Burst with Wrap (RBSPI)

SPI Read Burst with Wrap (RBSPI) is similar to SPI

Quad I/O Read except the data will output continuously

within the burst length until a low-to-high transition on

CE#. To execute a SPI Read Burst with Wrap opera-

tion, drive CE# low, then send the Read Burst com-

mand cycle (ECH), followed by three address cycles,

and then three dummy cycles.

After the dummy cycle, the device outputs data on the

falling edge of the SCK signal starting from the speci-

fied address location. The data output stream is contin-

uous through all addresses until terminated by a low-to-

high transition on CE#.

During RBSPI, the internal address pointer automati-

cally increments until the last byte of the burst is

reached, then it wraps around to the first byte of the

burst. All bursts are aligned to addresses within the

burst length, see Table 5-3. For example, if the burst

length is eight Bytes, and the start address is 06h, the

burst sequence would be: 06h, 07h, 00h, 01h, 02h,

03h, 04h, 05h, 06h, etc. The pattern repeats until the

command is terminated by a low-to-high transition on

CE#.

During this operation, blocks that are Read-locked will

output data 00H.

CE#

SIO0

SCK 012345678 12

MODE 3

MODE 0

91011

25119 F51.0

SIO[3:1]

1513 14

DIN

Note: SIO[3:1] must be driven V IH.

TABLE 5-3: BURST ADDRESS RANGES

Burst Length Burst Address Ranges

8 Bytes 00-07H, 08-0FH, 10-17H, 18-1FH...

16 Bytes 00-0FH, 10-1FH, 20-2FH, 30-3FH...

32 Bytes 00-1FH, 20-3FH, 40-5FH, 60-7FH...

64 Bytes 00-3FH, 40-7FH, 80-BFH, C0-FFH

 2013 Microchip Technology Inc. Advance Information DS25119C-page 21

SST26VF064B / SST26VF064BA

5.12 SPI Dual-Output Read

The SPI Dual-Output Read instruction supports up to

104 MHz frequency. Initiate SPI Dual-Output Read by

executing an 8-bit command, 3BH, followed by address

bits A[23-0] and a dummy byte. CE# must remain

active low for the duration of the SPI Dual-Output Read

operation. See Figure 5-13 for the SPI Quad Output

Read sequence.

Following the dummy byte, the SST26VF064B/064BA

outputs data from SIO[1:0] starting from the specified

address location. The de vice continually streams data

output through all addresses u ntil terminated by a low-

to-high transition on CE#. The internal address pointer

automatically increments until the highest memory

address is reached, at which point the address po inter

returns to the begi nn i n g of the address space.

FIGURE 5-13: FAST READ, DUAL-OUTPUT SEQUENCE

5.13 SPI Dual I/O Read

The SPI Dual I/O Read (SDIOR) instruction supports

up to 80 MHz frequency. Initiate SDIOR by executing

an 8-bit command, BBH. The device then switches to

2-bit I/O mode for address bits A[23-0], followed by the

Set Mode configuration bits M[7:0], and two dummy

bytes.CE# must remain active low for the duration of

the SPI Dual I/O Read. See Figure 5-14 for the SPI

Dual I/O Read sequence.

Following the dummy bytes, the SST26VF064B/064BA

outputs data from the specified address location. The

device continually streams data output through all

addresses until terminated by a low-to-high transition

on CE#. The internal address pointer automatically

increments until the highest memory address is

reached, at which point the address pointer returns to

the beginning of the address space.

The Set Mode Configu ration bit M[7:0] indicates if the

next instruction cycle is another SPI Dual I/O Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another SDIOR com-

mand, BBH, and does not require the op-code to be

entered again. The host may set the next SDIOR cycle

by driving CE# low , then sending the two-bit wide input

for address A[23:0], followed by the Set Mode configu-

ration bits M[7:0], and two dummy cycles. Af ter the two

dummy cycles, the device outputs the data starting

from the specified address location. There are no

restrictions on address location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Rese t Qua d I/O command, FFH. Se e Fig-

ure 5-15 for the SPI Dual I/O Read sequence when

M[7:0] = AXH.

CE#

SIO0

SCK 012345678 31 32

MODE 3

MODE 0 15 16 23

3BH

25119 F52.3

39 40 41

A[23:16] A[15:8] A[7:0]

b6 b5 b6 b5

SIO1

Address

OP Code Data

Byte 0

Dummy Data

Byte N

b3 b1 b3 b1

b7 b4 b7 b4

b2 b0 b2 b0

MSB

Note: MSB = Most Significant Bit.

SST26VF064B / SST26VF064BA

DS25119C-page 22 Advance Information  2013 Microchip Technology Inc.

FIGURE 5-14: SPI DUAL I/O READ SEQUENCE

FIGURE 5-15: BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH

753

642

CE#

SIO0

SCK 012345678 16 17

MODE 3

MODE 0

91011

25119 F53.1

SIO1

A[23:16]

1513 14 23

1918 2220 21

642

A[15:8] A[7:0] M[7:0]

753

CE#(cont’)

SIO0(cont’)

SCK(cont’)

23 24 32 33

2825 26 27

SIO1(cont’)

Byte 0

3129 30 39

3534 3836 37

642

Byte 1 Byte 2 Byte 3

206

317

MSB MSB MSB

MSB

I/O Switches from Input to Output

BBH

Note: MSB= Most Significant Bit, LSB = Least Significant Bit

753

MODE 3

MODE 0

642

CE#

SIO0

SCK 089

412 3

25119 F54.1

SIO1

A[23:16]

756 15

1110 1412 13

642

A[15:8] A[7:0] M[7:0]

753

CE#(cont’)

SIO0(cont’)

SCK(cont’)

15 16 24 25

2017 18 19

SIO1(cont’)

Byte 0

2321 22 31

2726 3028 29

642

Byte 1 Byte 2 Byte 3

206

317

MSB MSB MSB

MSB

75753

4642

MSB

I/O Switches from Input to Output

I/O Switch

Note: MSB= Most Significant Bit, LSB = Least Significant Bit

 2013 Microchip Technology Inc. Advance Information DS25119C-page 23

SST26VF064B / SST26VF064BA

5.14 JEDEC-ID Read (SPI Protocol)

Using traditional SPI protocol, the JEDEC-ID Read

instruction identifies the device as SST26VF064B/

064BA and the manufacturer as Microchip®. To exe-

cute a JECEC-ID operation the host drives CE# low

then sends the JEDEC-ID command cycle (9FH).

Immediately following the command cycle,

SST26VF064B/064BA output data on the falling edge

of the SCK signal. The data output stream is continu-

ous until terminated by a low-to-high transition on CE#.

The device outputs three bytes of data: manufacturer,

device type, and device ID, see Table 5-4. See Figure

5-16 for instruction sequence.

FIGURE 5-16: JEDEC-ID SEQUENCE (SPI)

5.15 Read Quad J-ID Read (SQI

Protocol)

The Read Quad J-ID Read instruction identifies the

device as SST26VF064B/064 BA and ma nufacturer as

Microchip. To execute a Quad J-ID operation the host

drives CE# low and then sends the Quad J-ID com-

mand cycle (AFH). Each cycle is two nibbles (clocks)

long, most significant nibble first.

Immediately following the command cycle and one

dummy cycle, SST26VF064B/064BA output data on

the falling edge of the SCK signal. The data output

stream is continuous until terminated by a low-to-high

transition of CE#. The device outputs three bytes of

data: manufacturer, device type, and device ID, see

Table 5-4. See Figure 5-17 for instruction sequence.

FIGURE 5-17: QUAD J-ID READ SEQUENCE

TABLE 5-4: DEVICE ID DATA OUTPUT

Product Manufacturer ID (Byte 1)

Device ID

Device Type (Byte 2) Device ID (Byte 3)

SST26VF064B/064BA BFH 26H 43H

26 Device ID

25119 F38.0

CE#

SCK 012345678

HIGH IMPEDANCE

15 1614 28 29 30 31

MODE 3

MODE 0

MSBMSB

9 10111213 1718 32 34

19 20 21 22 23 3324 25 26 27

BFH Device ID

Dummy BFH

MSN LSN

26H

26H N

25119 F55.0

012

SCK

SIO(3:0)

CE#

C1C0 X X H0 L0 H1 L1 H0 L1H1L0 HN LN

78 111091312 N

MODE 3

MODE 0

3456

H2 L2

Note: MSN = Most significant Nibble; LSN= Least Significant Nibble. C{1:0]=AFH

SST26VF064B / SST26VF064BA

DS25119C-page 24 Advance Information  2013 Microchip Technology Inc.

5.16 Serial Flash Discoverable

Parameters (SFDP)

The Serial Flash Discoverable Parameters (SFDP)

contain information describing the characteristics of the

device. This allows device-independent, JEDEC ID-

independent, and forward/backward compatible soft-

ware support for all future Serial Flash device families.

See Table 11-1 on page 59 for address and data val-

ues.

Initiate SFDP by execut ing an 8-bit command, 5AH, fol-

lowed by address bits A[23-0] and a dummy byte. CE#

must remain active low for the duration of the SFDP

cycle. For the SFDP sequence, see Figure 5-18.

FIGURE 5-18: SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE

5.17 Sector-Erase

The Sector-Erase instruction clears all bits in the

selected 4 KByte sector to ‘1,’ but it does not change a

protected memory area. Prior to any write operation,

the Write-Enable (WREN) instruction must be exe-

cuted.

To execute a Sector-Erase operation, the host drives

CE# low, then sends the Sector Erase command cycle

(20H) and three address cycles, and then drives CE#

high. Address bits [AMS:A12] (AMS = Most Significant

Address) determine the sector address (SAX); the

remaining address bits can be VIL or VIH. To identify the

completion of the internal, self-timed, Write operation,

poll the BUSY bit in the S tatus register , or wait TSE. See

Figures 5-19 and 5-20 for the Sector-Erase sequen ce.

FIGURE 5-19: 4 KBYTE SECTOR-ERASE SEQUENCE– SQI MODE

FIGURE 5-20: 4 KBYTE SECTOR-ERASE SEQUENCE (SPI)

25119 F56.0

CE#

SCK

ADD.

012345678

ADD. ADD.5A

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63 64

N+2 N+3 N+4

NN+1

MSB

MODE 0

MODE 3

DOUT DOUT DOUT DOUT

71 72

DOUT

25119 F07.0

MODE 3 0 1

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

A5 A4

MSN LSN

A3 A2

A1 A0

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 20H

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

25119 F57.0

MSBMSB

 2013 Microchip Technology Inc. Advance Information DS25119C-page 25

SST26VF064B / SST26VF064BA

5.18 Block-Erase

The Block-Erase instruction clears all bits in the

selected block to ‘1’. Block sizes can be 8 KByte, 32

KByte or 64 KByte depending on address, see Figure

3-1, Memory Map, for details. A Block-Erase instruction

applied to a protected memory area will be ignored.

Prior to any write operation, execute the WREN instruc-

tion. Keep CE# active low for the duration of an y com-

mand sequence.

To execute a Block-Erase operation, the host drives

CE# low then sends the Block-Erase command cycle

(D8H), three address cycles, then drives CE# high.

Address bits AMS-A13 determine the block address

(BAX); the remaining address bits can be VIL or VIH. For

32 KByte blocks, A14:A13 can be VIL or VIH; for 64

KByte blocks, A15:A13 can be VIL or VIH. Poll the BUSY

bit in the S t atus register , or wait TBE, for the completion

of the internal, se lf-timed, Block-Erase operation. See

Figures 5-21 and 5-22 for the Block-Erase sequence.

FIGURE 5-21: BLOCK-ERASE SEQUENCE (SQI)

FIGURE 5-22: BLOCK-ERASE SEQUENCE (SPI)

25119 F08.0

MODE 3 0 1

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

A5 A4

MSN LSN

A3 A2

A1 A0

Note: MSN = Most Significant Nibble,

LSN = Least Significant Nibble

C[1:0] = D8H

CE#

SCK

ADDR

012345678

ADDR ADDR

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

25119 F58.0

MSB MSB

SST26VF064B / SST26VF064BA

DS25119C-page 26 Advance Information  2013 Microchip Technology Inc.

5.19 Chip-Erase

The Chip-Erase instruction clears all bits in the de vice

to ‘1.’ The Chip-Erase instruction is ignored if any of the

memory area is protected. Prior to any write operation,

execute the WREN instruction.

To execute a Chip-Erase operation, the host drives

CE# low , sends the Chip-Erase command cycle (C7H),

then drives CE# high. Poll the BUSY bit in the Status

self-timed, Write operation. See Figures 5-23 and 5-24

for the Chip Erase sequence.

FIGURE 5-23: CHIP-ERASE SEQUENCE (SQI)

FIGURE 5-24: CHIP-ERASE SEQUENCE (SPI)

25119 F09.1

MODE 3 0 1

SCK

SIO(3:0)

CE#

MODE 0

Note: C[1:0] = C7H

CE#

SCK 01234567

HIGH IMPEDANCE

MODE 0

MODE 3

25119 F59.0

MSB

 2013 Microchip Technology Inc. Advance Information DS25119C-page 27

SST26VF064B / SST26VF064BA

5.20 Page-Program

The Page-Program instruction programs up to 256

Bytes of data in the memory, and supports both SPI

and SQI protocols. The data for the selected page

address must be in the erased state (FFH) before initi-

ating the Page-Program operation. A Page-Program

applied to a protected memory area will be ignored.

Prior to the program operation, execute the WREN

instruction.

To execute a Page-Program op eration , the host d rives

CE# low then sends the Page Program command cycle

(02H), three address cycles follow ed by the data to be

programmed, th en drives CE# high. The programme d

data must be between 1 to 256 Bytes and in whole Byte

increments; sending less than a full Byte will cause the

partial Byte to be ignored. Poll the BUSY bit in the Sta-

tus register, or wait TPP, for the completion of the inter-

nal, self-timed, Write operation. See Figures 5-25 and

5-26 for the Page-Program sequence.

When executing Page-Program, the memory range for

the SST26VF064B/064BA is divided into 256 Byte

page boundaries. The device handles shifting of more

than 256 Bytes of data by maintaining the last 256

Bytes of data as the correct data to be programme d. If

the target address for the Page-Pro gram instruction is

not the beginning of the page boundary (A[7:0] are not

all zero), and the number of bytes of data input exceeds

or overlaps the end of the address of the page bound-

ary , the excess data inputs wrap around and will be pro-

grammed at the start of that target page.

FIGURE 5-25: PAGE-PROGRAM SEQUENCE (SQI)

FIGURE 5-26: PAGE-PROGRAM SEQUENCE (SPI)

25119 F10.1

MODE 3 0

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

A5 A4

MSN LSN

A3 A2

A1 A0

H0 L0

H1 L1

H2 L2 HN LN

Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 255

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

C[1:0] = 02H

25119 F60.1

CE#

SCK

ADD.

012345678

ADD. ADD. Data Byte 0

HIGH IMPEDANCE

15 16 23 24 31 32 39

MODE 0

MODE 3

MSBMSB

MSB LSB

CE#(cont’)

SO(cont’)

SI(cont’)

SCK(cont’)

40 41 42 43 44 45 46 47 48

Data Byte 1

HIGH IMPEDANCE

MSBMSB

MSB LSB

50 51 52 53 54 55

2072

Data Byte 2

2073

2074

2075

2076

2077

2078

2079

Data Byte 255

LSBLSB

LSB LSB

SST26VF064B / SST26VF064BA

DS25119C-page 28 Advance Information  2013 Microchip Technology Inc.

5.21 SPI Quad Page-Program

The SPI Quad Page-Program instruction pr ograms up

to 256 Bytes of data in the memory. The data for the

selected page address must be in the erased state

(FFH) before initiating the SPI Quad Page-Program

operation. A SPI Quad Page-Program applied to a pro-

tected memory area will be ignored. SST26VF064B

requires the ICO bit in the configuration register to be

set to ‘1’ prior to executing the comman d. Prior to the

program operation, execu t e the WREN instruction.

To execute a SPI Quad Page-Program operation, the

host drives CE# low then sends the SPI Quad Page-

Program command cycle (32H), three address cycles

followed by the data to be programmed, then drives

CE# high. The programmed data must be between 1 to

256 Bytes and in whole Byte increments. The com-

mand cycle is eight clocks long, the address and data

cycles are each two clocks long, most significant bit

first. Poll the BUSY bit in the S tatus register , or wait TPP,

for the completion of the internal, self-timed, Write

operation.See Figure 5-27.

When executing SPI Quad Page-Program, the memory

range for the SST26VF064B/064BA is divided into 256

Byte page boundaries. The device handles shifting of

more than 256 Bytes of data by maintaining the last 256

Bytes of data as the correct data to be programme d. If

the target address for the SPI Quad Page-Program

instruction is not the beginning of the page boundary

(A[7:0] are not all zero), and the of bytes of data input

exceeds or overlaps the end of the address of the page

boundary, the excess data inputs wrap around and will

be programmed at the start of that target page.

FIGURE 5-27: SPI QUAD PAGE-PROGRAM SEQUENCE

5.22 Write-Suspend and Write-Resume

Write-Suspend allows the interruption of Sector-Erase,

Block-Erase, SPI Quad Page-Program, or Page-Pro-

gram operations in order to erase, program, or read

data in another portion of memory. The original opera-

tion can be continued with the Write-Resume com-

mand. This operation is supported in both SQI and SPI

protocols.

Only one write operation can be suspended at a time;

if an operation is already suspended, the device will

ignore the Write-Suspend command. Write-Suspend

during Chip-Erase is ignored; Chip-Erase is not a valid

command while a write is suspended. The Write-

Resume command is igno red until any write o peration

(Program or Erase) initi ated durin g the Write-Suspend

is complete. The device requires a minimum of 500 µs

between each Write-Suspend command.

5.23 Write-Suspend During Sector-

Erase or Block-Erase

Issuing a Write-Suspend instruction during Sector-

Erase or Block-Erase allows the host to program or

read any sector that was not being erased. The device

will ignore any programming commands pointing to the

suspended sector(s). Any attempt to read from the sus-

pended sector(s) will output unknown data because the

Sector- or Block-Erase will be incomplete.

To execute a Write-Suspend operation, the host drives

CE# low, sends the Write Suspend command cycle

(B0H), then drives CE# high. The Status register indi-

cates that the erase has been suspended by changing

the WSE bit from ‘0’ to ‘1,’ but the device will not accept

another command until it is ready. To determine when

the device will accept a new command, p oll the BUSY

bit in the Status register or wait TWS.

A20A16A12

A8 A4 A0 b4 b0

CE#

SIO0

SCK 012345678 16 17

MODE 3

MODE 0 91011

32H

25119 F61.0

SIO1

SIO2

SIO3

Address Data

Byte 1

1513 14

A21 A17A13

A9 A5 A1 b5 b1 b5 b1 b5 b1

A22 A18A14

A10A6 A2 b6 b2 b6 b2 b6 b2

A23 A19A15 A11

A7 A3 b7 b3 b7 b3 b7 b3

Data

Byte 0 Data

Byte

255

MSN LSN

b4 b0 b4 b0

 2013 Microchip Technology Inc. Advance Information DS25119C-page 29

SST26VF064B / SST26VF064BA

5.24 Write Suspend During Page

Programming or SPI Quad Page

Programming

Issuing a Write-Suspend instruction during Page Pro-

gramming allows the h ost to erase or read any sector

that is not being programmed. Erase commands point-

ing to the suspended sector(s) will be ignored. Any

attempt to read from the suspended page will output

unknown data because the program will be incomplete.

To execute a Write Suspend operation, the ho st drives

CE# low, sends the Write Suspend command cycle

(B0H), then drives CE# high. The Status regi ster indi-

cates that the programming has been suspended by

changing the WSP bit from ‘0’ to ‘1,’ but the device will

not accept another command until it is ready. To deter-

mine when the device will accept a new command, poll

the BUSY bit in the Status register or wait TWS.

5.25 Write-Resume

Writ e-Resume rest arts a W rite command that was sus-

pended, and changes the suspend status bit in the S ta-

tus register (WSE or WSP) back to ‘0’.

To execute a Write-Resume operation, the host d rives

CE# low, sends the Write Resume command cycle

(30H), then drives CE# high. To determine if the inter-

nal, self-timed Write operation completed, poll the

BUSY bit in the Status register, or wait the specified

time TSE, TBE or TPP for Sector-Erase, Block-Erase, or

Page-Programming, respectively. The total write time

before suspend and after resume will not exceed the

uninterrupted write times TSE, TBE or TPP.

5.26 Read Security ID

The Read Security ID operation is supported in both

SPI and SQI modes. To execute a Read Security ID

(SID) operation in SPI mode, the host drives CE# low,

sends the Read Security ID command cycle (88H), two

address cycles, and then one dummy cycle. To execute

a Read Security ID operation in SQI mode, the host

drives CE# low and then sends the Read Security ID

command, two address cycles, and three dummy

cycles.

After the dummy cycles, the device output s data on the

falling edge of the SCK signal, starting from the speci-

fied address location. The data output stream is contin-

uous through all SID addresses until terminated by a

low-to-high transition on CE#. See Table 5-5 for the

Security ID address range.

5.27 Program Security ID

The Program Security ID instruction programs one to

2040 Bytes of data in the user-programmable, Security

ID space. This Security ID space is one-time program-

mable (OTP). The device ignores a Program Security

ID instruction pointing to an invalid or protected

address, see Table 5-5. Prior to the program operation,

execute WREN.

To execute a Program SID operation, the host drives

CE# low, sends the Program Security ID command

cycle (A5H), two address cycles, the data to be pro-

grammed, then drives CE# high. The programmed data

must be between 1 to 256 Bytes and in whole Byte

increments.

The device handles sh ifting of more than 256 Bytes of

data by maintaining the last 256 Bytes of data as the

correct data to be programmed. If the target address for

the Program Security ID instruction is not the beginning

of the page boundary, and the number of data input

exceeds or overlaps the end of the address of the page

boundary, the excess data inputs wrap around and will

be programmed at the start of that target page.

The Program Security ID operation is supported in both

SPI and SQI mode. To determine the completion of the

internal, self-timed Program SID operation, poll the

BUSY bit in the software status register, or wait TPSID

for the completion of the internal self-timed Program

Security ID operation.

TABLE 5-5: PROGRAM SECURITY ID

Program Security ID Address Range

Unique ID Pre-Programmed at factory 0000 – 0007H

User Programmable 0008H – 07FFH

SST26VF064B / SST26VF064BA

DS25119C-page 30 Advance Information  2013 Microchip Technology Inc.

5.28 Lockout Security ID

The Lockout Security ID instruction prevents any future

changes to the Security ID, and is supported in both

SPI and SQI modes. Prior to the operation, execute

WREN.

To execute a Lockout SID, the host drives CE# low,

sends the Lockout Security ID command cycle (85H),

then drives CE# high. Poll the BUSY bit in the software

status register, or wait TPSID, for the completion of the

Lockout Security ID operation.

5.29 Read-Status Register (RDSR) and

Read-Configuration Register

(RDCR)

The Read-Status Register (RDSR) and Read-Configu-

ration Register (RDCR) commands output the contents

of the Status and Configuration registers. These com-

mands function in both SPI and SQI modes. The S tatus

operation. When a Write is in progress, poll the BUSY

bit before sending any new commands to assure that

the new commands are properly received by the

device.

To Read the Status or Configuration registers, the host

drives CE# low, then sends the Read-Status-Register

command cycle (05H) or the Read Configuration Reg-

ister command (35H). A dummy cycle is required in

SQI mode. Immediately after the command cycle, the

device outputs data on the falling edge of the SCK sig-

nal. The data output stream continues until terminated

by a low-to-high transition on CE#. See Figures 5-28

and 5-29 for the instruction sequence.

FIGURE 5-28: READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER

SEQUENCE (SQI)

FIGURE 5-29: READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER

SEQUENCE (SPI)

25119 F11.1

MODE 3 0

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

MSN LSN

H0 L0

Dummy Data Byte Data Byte Data Byte

Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, C[1:0]=05H or 35H

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

25119 F62.0

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05 or 35

MODE 0

HIGH IMPEDANCE

Status

Data Out

MSB

 2013 Microchip Technology Inc. Advance Information DS25119C-page 31

SST26VF064B / SST26VF064BA

5.30 Write-Status Register (WRSR)

The Write-Status Register (WRSR) command writes

new values to the C onfiguration register. To execute a

Write-Status Register operation, the host drives CE#

low, then sends the Write-Status Register command

cycle (01H), two cycles of data, and then drives CE#

high. Values in the second data cycle will b e accepted

by the device. See Figures 5-30 and 5-31.

FIGURE 5-30: WRITE-STATUS-REGISTER SEQUENCE (SQI)

FIGURE 5-31: WRITE-STATUS-REGISTER SEQUENCE (SPI)

25119 F63.1

MODE 3 0 1

SCK

SIO[3:0]

CE#

C1 C0

MODE 0

XX XX

MSN LSN

H0 L0

Status

Byte

Command

Config-

uration

Byte

Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, XX = Don’t Care, C[1:0]=01H

25119 F64.1

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

BYTE

MSBMSB 01

SCK

CE#

0 1 2 3 4 5 6 7 8 9 101112131415

CONFIGURATION

BYTE

76543210

MSB

16 17 18 19 20 21 22 23

XX XX XX XX XX XX XX

Note: XX = Don’t Care

SST26VF064B / SST26VF064BA

DS25119C-page 32 Advance Information  2013 Microchip Technology Inc.

5.31 Write-Enable (WREN)

The Write Enable (WREN) instruction sets the Write-

Enable-Latch bit in the Status register to ‘1,’ allowing

Write operations to occur. The WREN instruction must

be executed prior to any of the following operations:

Sector Erase, Block Erase, Chip Erase, Page Program,

Program Security ID, Lockout Security ID, Write Block-

Protection Register, Lock-Down Block-Protection Reg-

ister , Non-V olatile Write-Lock Lock-Down Register , SPI

Quad Page program, and Write-Status Register. To

execute a Write Enable the host drives CE# low then

sends the Write Enable command cycle (06H) then

drives CE# high. See Figures 5-32 and 5-33 for the

WREN instruction sequence.

FIGURE 5-32: WRITE-ENABLE SEQUENCE (SQI)

FIGURE 5-33: WRITE-ENABLE SEQUENCE (SPI)

25119 F12.1

MODE 3 0 1

SCK

SIO[3:0]

CE#

MODE 0

CE#

SCK 01234567

HIGH IMPEDANCE

MODE 0

MODE 3

25119 F18.0

MSB

 2013 Microchip Technology Inc. Advance Information DS25119C-page 33

SST26VF064B / SST26VF064BA

5.32 Write-Disable (WRDI)

The Write-Disable (WRDI) instruction sets the Write-

Enable-Latch bit in the S tatus register to ‘0,’ preventing

Write operations. The WRDI instruction is ignore d dur-

ing any internal write operations. Any Write operation

started before executing WRDI will complete. Drive

CE# high before executing WRDI.

To execute a Write-Disable, the host drives CE# low,

sends the Write Disable command cycle (04H), then

drives CE# high. See Figures 5-34 and 5-35.

FIGURE 5-34: WRITE-DISABLE (WRDI) SEQUENCE (SQI)

FIGURE 5-35: WRITE-DISABLE (WRDI) SEQUENCE (SPI)

25119 F33.1

MODE 3 0 1

SCK

SIO(3:0)

CE#

MODE 0

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

25119 F19.0

MSB

SST26VF064B / SST26VF064BA

DS25119C-page 34 Advance Information  2013 Microchip Technology Inc.

5.33 Read Block-Protection Register

(RBPR)

The Read Block-Protection Register instruction outputs

the Block-Protection register data which determines

the protection status. To execute a Read Block-Protec-

tion Register operation, the host drives CE# low, and

then sends the Read Block-Protection Register com-

mand cycle (72H). A dummy cycle is required in SQI

mode.

After the command cycle, the device outputs data on

the falling edge of the SCK signal starting with the most

significant bit(s), see T able 5-6 for definitions of each bit

in the Block-Protection register. The RBPR command

does not wrap around. After all data has been output,

the device will output 0H until terminated by a low-to-

high transition on CE#. Figures 5-36 and 5-37.

FIGURE 5-36: READ BLOCK-PROTECTION REGISTER SEQUENCE (SQI)

FIGURE 5-37: READ BLOCK-PROTECTION REGISTER SEQUENCE (SPI)

25119 F34.2

MODE 3 0

SCK

SIO[3:0]

CE#

C1 C0

H0 L0

MSN LSN

H1 L1

H2 L2

H3 L3

H4 L4

HN LN

BPR [m:m-7] BPR [7:0]

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

Block-Protection Register (BPR), m = 143 for SST26VF064B/064BA, C[1:0]=72H

CE#

SIO0

SCK 012345678 32 33

MODE 3

MODE 0

15 16 23

72H

25119 F48.0

SIO

OP Code

Data Byte 0 Data Byte 1 Data Byte 2 Data Byte N

 2013 Microchip Technology Inc. Advance Information DS25119C-page 35

SST26VF064B / SST26VF064BA

5.34 Write Block-Protection Register

(WBPR)

The Write Block-Protection Register (WBPR) com-

mand changes the Block-Protection register data to

indicate the protection status. Execute WREN before

executing WBPR.

To execute a Write Block-Protection Register operation

the host drives CE# low , sends the Write Block-Protec-

tion Register command cycle (42H), sends 18 cycles of

data, and finally drives CE# high. Data input must be

most significant bit(s) first. See Table 5-6 for definitions

of each bit in the Block-Protection register . See Figures

5-38 and 5-39.

FIGURE 5-38: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SQI)

FIGURE 5-39: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SPI).

25119 F35.1

MODE 3 0

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

H0 L0

MSN LSN

H1 L1

H2 L2

H3 L3

H4 L4

H5 L5 HN LN

BPR [143:136] BPR [7:0]

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

Block-Protection Register (BPR) C[1:0]=42H

CE#

SCK

Data Byte0

012345678

Data Byte1 Data Byte2 Data ByteN

42H

15 16 23 24 31 32

MODE 0

MODE 3

OP Code

25119 F66.1

Note: C[1:0]=42H

SST26VF064B / SST26VF064BA

DS25119C-page 36 Advance Information  2013 Microchip Technology Inc.

5.35 Lock-Down Block-Protection

The Lock-Down Block-Protection Register instruction

prevents changes to the Block-Protection regi ster dur-

ing device operation. Lock-Down resets after power

cycling; this allows the Block-Protection register to be

changed. Execute WREN before initiating the Lock-

Down Block-Protection Register instruction.

To execute a Lock-Down Block-Protection Register, the

host drives CE# low , then sends the Lock-Down Block-

Protection Register command cycle (8DH), then drives

CE# high.

FIGURE 5-40: LOCK-DOWN BLOCK-PROTECTION REGISTER (SQI)

FIGURE 5-41: LOCK-DOWN BLOCK-PROTECTION REGISTER (SPI)

25119 F30.1

MODE 3 0 1

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

Note: C[1:0]=8DH

25119 F67.0

MODE 3 0 1

SCK

SIO0

CE#

MODE 0

234567

SIO[3:1]

 2013 Microchip Technology Inc. Advance Information DS25119C-page 37

SST26VF064B / SST26VF064BA

5.36 Non-Volatile Write-Lock Lock-

Down Register (nVWLDR)

The Non-Volatile Write-Lock Lock-Down Register

(nVWLDR) instruction controls the ability to change the

Write-Lock bits in the Block-Protection register. Exe-

cute WREN before initiating the nVWLDR instruction.

To execute nVWLDR, the host drives CE# low, then

sends the nVWLDR command cycle (E8H), followed by

18 cycles of data, and then drives CE# high.

After CE# goes high, the non-volatile bits are pro-

grammed and the programming time-out must com-

plete before any additional commands, other than

Read Status Register, can be entered. Poll the BUSY

bit in the St atus register, or wait TPP, for the completion

of the internal, se lf-timed, Write operation. Data inputs

must be most significant bit(s) first.

FIGURE 5-42: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)

FIGURE 5-43: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)

25119 F36.0

MODE 3 0

SCK

SIO(3:0)

CE#

MODE 0

H0 L0

MSN LSN

H1 L1

H2 L2

H3 L3

H4 L4

H5 L5 HN LN

BPR [m:m-7] BPR [7:0]

Note: MSN= Most Significant Nibble; LSN = Least Significant Nibble

Write-Lock Lock-Down Register (nVWLDR) m = 143

CE#

SCK

Data Byte0

012345678

Data Byte1 Data Byte2 Data ByteN

E8H

15 16 23 24 31 32

MODE 0

MODE 3

OP Code

25119 F69.1

SST26VF064B / SST26VF064BA

DS25119C-page 38 Advance Information  2013 Microchip Technology Inc.

5.37 Global Block-Protection Unlock

(ULBPR)

The Global Block-Protection Unlock (ULBPR) instruc-

tion clears all w rite-protection bits in the Block-Protec-

tion register, except for those bits that have been

locked down with the nVWLDR command. Execute

WREN before initiating the ULBPR instruction.

To execute a ULBPR instruction, the host drives CE#

low , then sends the ULBPR command cycle (98H), and

then drives CE# high.

FIGURE 5-44: GLOBAL BLOCK-PROTECTION UNLOCK (SQI)

FIGURE 5-45: GLOBAL BLOCK-PROTECTION UNLOCK (SPI)

25119 F20.1

MODE 3 0 1

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

Note: C[1:0]=98H

25119 F68.0

MODE 3 0 1

SCK

SIO0

CE#

MODE 0

234567

SIO[3:1]

 2013 Microchip Technology Inc. Advance Information DS25119C-page 39

SST26VF064B / SST26VF064BA

TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (1 OF 4)1

BPR Bits

Address Range Protected Block

SizeRead Lock Write Lock/

nVWLDR2

143 142 7FE000H - 7FFFFFH 8 KByte

141 140 7FC000H - 7FDFFFH 8 KByte

139 1387FA000H - 7FBFFFH 8 KByte

137 136 7F8000H - 7F9FFFH 8 KByte

135 134 006000H - 007FFFH 8 KByte

133 132 004000H - 005FFFH 8 KByte

131 130 002000H - 003FFFH 8 KByte

129 128000000H - 001FFFH 8 KByte

127 7F0000H - 7F7FFFH 32 KByte

126 008000H - 00FFFFH 32 KByte

125 7E0000H - 7EFFFFH 64 KByte

124 7D0000H - 7DFFFFH 64 KByte

123 7C0000H - 7CFFFFH 64 KByte

122 7B0000H - 7BFFFFH 64 KByte

121 7A0000H - 7AFFFFH 64 KByte

120 790000H - 79FFFFH 64 KByte

119 780000H - 78FFFFH 64 KByte

118770000H - 77FFFFH 64 KByte

117 760000H - 76FFFFH 64 KByte

116 750000H - 75FFFFH 64 KByte

115 740000H - 74FFFFH 64 KByte

114 730000H - 73FFFFH 64 KByte

113 720000H - 72FFFFH 64 KByte

112 710000H - 71FFFFH 64 KByte

111 700000H - 70FFFFH 64 KByte

110 6F0000H - 6FFFFFH 64 KByte

109 6E0000H - 6EFFFFH 64 KByte

1086D0000H - 6DFFFFH 64 KByte

107 6C0000H - 6CFFFFH 64 KByte

106 6B0000H - 6BFFFFH 64 KByte

105 6A0000H - 6AFFFFH 64 KByte

104 690000H - 69FFFFH 64 KByte

103 680000H - 68FFFFH 64 KByte

102 670000H - 67FFFFH 64 KByte

101 660000H - 66FFFFH 64 KByte

100 650000H - 65FFFFH 64 KByte

99 640000H - 64FFFFH 64 KByte

98630000H - 63FFFFH 64 KByte

97 620000H - 62FFFFH 64 KByte

96 610000H - 61FFFFH 64 KByte

95 600000H - 60FFFFH 64 KByte

94 5F0000H - 5FFFFFH 64 KByte

93 5E0000H - 5EFFFFH 64 KByte

SST26VF064B / SST26VF064BA

DS25119C-page 40 Advance Information  2013 Microchip Technology Inc.

92 5D0000H - 5DFFFFH 64 KByte

91 5C0000H - 5CFFFFH 64 KByte

90 5B0000H - 5BFFFFH 64 KByte

89 5 A0000H - 5AFFFFH 64 KByte

88 590000H - 59FFFFH 64 KByte

87580000H - 58FFFFH 64 KByte

86 570000H - 57FFFFH 64 KByte

85 560000H - 56FFFFH 64 KByte

84 550000H - 55FFFFH 64 KByte

83 540000H - 54FFFFH 64 KByte

82 530000H - 53FFFFH 64 KByte

81 520000H - 52FFFFH 64 KByte

80 510000H - 51FFFFH 64 KByte

79 500000H - 50FFFFH 64 KByte

784F0000H - 4FFFFFH 64 KByte

77 4E0000H - 4EFFFFH 64 KByte

76 4D0000H - 4DFFFFH 64 KByte

75 4C0000H - 4CFFFFH 64 KByte

74 4B0000H - 4BFFFFH 64 KByte

73 4A0000H - 4AFFFFH 64 KByte

72 490000H - 49FFFFH 64 KByte

71 480000H - 48FFFFH 64 KByte

70 470000H - 47FFFFH 64 KByte

69 460000H - 46FFFFH 64 KByte

68450000H - 45FFFFH 64 KByte

67 440000H - 44FFFFH 64 KByte

66 430000H - 43FFFFH 64 KByte

65 420000H - 42FFFFH 64 KByte

64 410000H - 41FFFFH 64 KByte

63 400000H - 40FFFFH 64 KByte

62 3F0000H - 3FFFFFH 64 KByte

61 3E0000H - 3EFFFFH 64 KByte

60 3D0000H - 3DFFFFH 64 KByte

59 3C0000H - 3CFFFFH 64 KByte

583B0000H - 3BFFFFH 64 KByte

57 3A0000H - 3AFFFFH 64 KByte

56 390000H - 39FFFFH 64 KByte

55 380000H - 38FFFFH 64 KByte

54 370000H - 37FFFFH 64 KByte

53 360000H - 36FFFFH 64 KByte

52 350000H - 35FFFFH 64 KByte

51 340000H - 34FFFFH 64 KByte

50 330000H - 33FFFFH 64 KByte

TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (CONTINUED) (2 OF

BPR Bits

Address Range Protected Block

SizeRead Lock Write Lock/

nVWLDR2

 2013 Microchip Technology Inc. Advance Information DS25119C-page 41

SST26VF064B / SST26VF064BA

49 320000H - 32FFFFH 64 KByte

48310000H - 31FFFFH 64 KByte

47 300000H - 30FFFFH 64 KByte

46 2F0000H - 2FFFFFH 64 KByte

45 2E0000H - 2EFFFFH 64 KByte

44 2D0000H - 2DFFFFH 64 KByte

43 2C0000H - 2CFFFFH 64 KByte

42 2B0000H - 2BFFFFH 64 KByte

41 2A0000H - 2AFFFFH 64 KByte

40 290000H - 29FFFFH 64 KByte

39 280000H - 28FFFFH 64 KByte

38270000H - 27FFFFH 64 KByte

37 260000H - 26FFFFH 64 KByte

36 250000H - 25FFFFH 64 KByte

35 240000H - 24FFFFH 64 KByte

34 230000H - 23FFFFH 64 KByte

33 220000H - 22FFFFH 64 KByte

32 210000H - 21FFFFH 64 KByte

31 200000H - 20FFFFH 64 KByte

30 1F0000H - 1FFFFFH 64 KByte

29 1E0000H - 1EFFFFH 64 KByte

281D0000H - 1DFFFFH 64 KByte

27 1C0000H - 1CFFFFH 64 KByte

26 1B0000H - 1BFFFFH 64 KByte

25 1A0000H - 1AFFFFH 64 KByte

24 190000H - 19FFFFH 64 KByte

23 180000H - 18FFFFH 64 KByte

22 170000H - 17FFFFH 64 KByte

21 160000H - 16FFFFH 64 KByte

20 150000H - 15FFFFH 64 KByte

19 140000H - 14FFFFH 64 KByte

18130000H - 13FFFFH 64 KByte

17 120000H - 12FFFFH 64 KByte

16 110000H - 11FFFFH 64 KByte

15 100000H - 10FFFFH 64 KByte

14 0F0000H - 0FFFFFH 64 KByte

13 0E0000H - 0EFFFFH 64 KByte

12 0D0000H - 0DFFFFH 64 KByte

11 0C0000H - 0CFFFFH 64 KByte

10 0B0000H - 0BFFFFH 64 KByte

9 0A0000H - 0AFFFFH 64 KByte

8090000H - 09FFFFH 64 KByte

7080000H - 08FFFFH 64 KByte

TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (CONTINUED) (3 OF

BPR Bits

Address Range Protected Block

SizeRead Lock Write Lock/

nVWLDR2

SST26VF064B / SST26VF064BA

DS25119C-page 42 Advance Information  2013 Microchip Technology Inc.

6 070000H - 07FFFFH 64 KByte

5 060000H - 06FFFFH 64 KByte

4 050000H - 05FFFFH 64 KByte

3 040000H - 04FFFFH 64 KByte

2 030000H - 03FFFFH 64 KByte

1 020000H - 02FFFFH 64 KByte

0 010000H - 01FFFFH 64 KByte

1. The default state after a power-on reset is write-protected BPR[14 3:0] = 5555 FFF FFFFF FFFFFFFF FFF FFFFF FFFFFFFF

2. nVWLDR bits are one-time-programmable. Once a nVWLDR bit is set, the protection state of that particular block is perma-

nently write-locked.

TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (CONTINUED) (4 OF

BPR Bits

Address Range Protected Block

SizeRead Lock Write Lock/

nVWLDR2

 2013 Microchip Technology Inc. Advance Information DS25119C-page 43

SST26VF064B / SST26VF064BA

6.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-

mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-

tional oper ation o f the device at the se conditions or conditions great er than tho se define d in the o perat ional

sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may

affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Pack age Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Output shorted for no more than one second. No more than one output shorted at a time.

TABLE 6-1: OPERATING RANGE

Range Ambient Temp VDD

Industrial -40°C to +85°C 2.7-3.6V

TABLE 6-2: AC CONDITIONS OF TEST1

1. See Figure 8-5

Input Rise/Fall Time Output Load

3ns CL = 30 pF

SST26VF064B / SST26VF064BA

DS25119C-page 44 Advance Information  2013 Microchip Technology Inc.

6.1 Power-Up Specifications

All functionalities and DC specifications are specified

for a VDD ramp rate of greater than 1V per 100 ms (0V

to 3.0V in less than 300 ms). See Table 6-3 and Figure

6-1 for more information.

When VDD drops from the operating voltage to below

the minimum VDD threshold at powe r-down, all opera-

tions are disabled and the device does not respond to

commands. Data corruption may result if a power-down

occurs while a Write-Registers, program, or erase

operation is in progress. See Figure 6-2.

FIGURE 6-1: POWER-UP TIMING DIAGRAM

TABLE 6-3: RECOMMENDED SYSTEM POWER-UP/DOWN TIMINGS

Symbol Parameter Minimum Max Units Condition

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this par ameter.

VDD Min to Read Operation 100 µs

TPU-WRITE1VDD Min to Write Operation 100 µs

TPD1Power-down Duration 100 ms

VOFF VDD off time 0.3 V0V recommended

Time

VDD Min

VDD Max

VDD

Device fully accessible

TPU-READ

TPU-WRITE

Chip selection is not allowed.

Commands may not be accepted or properly

interpreted by the device.

25119 F27.0

 2013 Microchip Technology Inc. Advance Information DS25119C-page 45

SST26VF064B / SST26VF064BA

FIGURE 6-2: POWER-DOWN AND VOLTAGE DROP DIAGRAM

Device

Access

Allowed

TPD

TPU

No Device Access Allowed

Time

VDD Min

VDD Max

VDD

25119 F72.0

VOFF

SST26VF064B / SST26VF064BA

DS25119C-page 46 Advance Information  2013 Microchip Technology Inc.

7.0 DC CHARACTERISTICS

TABLE 7-1: DC OPERATING CHARACTERISTICS (VDD = 2.7 - 3.6V)

Symbol Parameter

Limits

Test ConditionsMin Typ Max Units

IDDR1 Read Current 815 mA VDD=VDD Max,

CE#=0.1 V DD/0.9 VDD@40 MHz,

SO=open

IDDR2 Read Current 20 mA VDD = VDD Max,

CE#=0.1 V DD/0.9 VDD@104 MHz,

SO=open

IDDW Program and Erase Cur-

rent 25 mA VDD Max

ISB Standby Current 15 45 µA CE#=VDD, V IN=VDD or VSS

ILI Input Leakage Current 2µAVIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 2µAVOUT=G ND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8VVDD=VDD Min

VIH Input High Voltage 0.7 VDD VVDD=VDD Max

VOL Output Low Voltage 0.2 VIOL=100 µA, VDD=VDD Min

VOH Output High V oltage VDD-0.2 VIOH=-100 µA, VDD=VDD Min

TABLE 7-2: CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)

P arameter Description Test Condition Maximum

COUT1

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

Output Pin Capacitance VOUT = 0V8 pF

CIN1Input Capacitance VIN = 0V6 pF

TABLE 7-3: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

Endurance 100,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

TABLE 7-4: WRITE TI MING PARAMETERS (VDD = 2.7 - 3.6V)

Symbol Parameter Minimum Maximum Units

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

TPP Page-Program 1.5 ms

TPSID Program Security-ID 1.5 ms

TWS Write-Suspend Latency 25 µs

TWpen Write-Protection Enable Bit Latency 25 ms

 2013 Microchip Technology Inc. Advance Information DS25119C-page 47

SST26VF064B / SST26VF064BA

8.0 AC CHARACTERISTICS

FIGURE 8-1: HOLD TIMING DIAGRAM

TABLE 8-1: AC OPERATING CHARACTERISTICS (VDD = 2.7 - 3.6V)

Symbol Parameter

Limits - 40 MHz Limits - 80 MHz Limits - 104 MHz

UnitsMin Max Min Max Min Max

FCLK Serial Clock Frequency 40 80 104 MHz

TCLK Serial Clock Period 25 12.5 9.6 ns

TSCKH Serial Clock High Time 11 5.5 4.5 ns

TSCKL Serial Clock Low Time 11 5.5 4.5 ns

TSCKR1

1. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements

Serial Clock Rise Time (slew rate) 0.1 0.1 0.1 V/ns

TSCKF1Serial Clock Fall Time (slew rate) 0.1 0.1 0.1 V/ns

TCES2

2. Relative to SCK.

CE# Active Setup Time 855ns

TCEH2CE# Active Hold Time 855ns

TCHS2CE# Not Active Setup Time 855ns

TCHH2CE# Not Active Hold Time 855ns

TCPH CE# High Time 25 12.5 12 ns

TCHZ CE# High to High-Z Output 19 12.5 12 ns

TCLZ SCK Low to Low-Z Output 000ns

THLS HOLD# Low Setup Time 855ns

THHS HOLD# High Setup Time 855ns

THLH HOLD# Low Hold Time 855ns

THHH HOLD# High Hold Time 855ns

THZ HOLD# Low-to-High-Z Output 888ns

TLZ HOLD# High-to-Low-Z Output 888ns

TDS Data In Setup Time 333ns

TDH Data In Hold T ime 444ns

TOH Output Hold from SCK Change 000ns

TVOutput Valid from SCK 8/5 3

3. 30 pF/10 pF

8/5 38/5 3ns

THZ TLZ

THHH THLS THHS

25119 F43.1

HOLD#

CE#

SCK

THLH

SST26VF064B / SST26VF064BA

DS25119C-page 48 Advance Information  2013 Microchip Technology Inc.

FIGURE 8-2: SERIAL INPUT TIMING DIAGRAM

FIGURE 8-3: SERIAL OUTPUT TIMING DIAGRAM

FIGURE 8-4: RESET TIMING DIAGRAM

TABLE 8-2: RESET TIMING PARAMETERS

TR(i) Parameter Minimum Maximum Units

TR(o) Reset to Read (non-data operation) 20 ns

TR(p) Reset Recovery from Program or Suspend 100 µs

TR(e) Reset Recovery from Erase 1ms

CE#

SIO[3:0]

SCK

MSB LSB

TDS TDH

TCHH TCES TCEH TCHS

TSCKR

TSCKF

TCPH

25119 F70.1

25119 F25.1

CE#

SIO[3:0]

SCK

MSB

TCLZ

TSCKH

TCHZ

TOH

TSCKL

LSB

25119 F14.0

MODE 3

CLK

SIO(3:0)

CE#

MODE 3

C1 C3 C2C0

MODE 0

MODE 3

MODE 0MODE 0

TCPH

Note: C[1:0] = 66H; C[3:2] = 99H

 2013 Microchip Technology Inc. Advance Information DS25119C-page 49

SST26VF064B / SST26VF064BA

FIGURE 8-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS

25119 F28.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (0.9VDD) for a logic ‘1’ and VILT (0.1VDD) for a logic ‘0’. Measure-

ment reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and

fall times (10% ↔ 90%) are <3 ns.

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

SST26VF064B / SST26VF064BA

DS25119C-page 50 Advance Information  2013 Microchip Technology Inc.

9.0 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

TABLE 9-1: PART MARKING

Ordering Number Marking On Part

SST26VF064B-104-5I-MF 26VF064B-I/MF

SST26VF064BA-104-5I-MF 26VF064B-I/MF

SST26VF064B-104-5I-SM 26VF064B-I/SM

SST26VF064BA-104-5I-SM 26VF064B-I/SM

SST26VF064B-104-5I-SO 26VF064B-I/SO

SST26VF064BA-104-5I-SO 26VF064B-I/SO

SST26VF064B-104-5I-TD 26VF064B-I/TD

SST26VF064BA-104-5I-TD 26VF064B-I/TD

PART NO. XXX

Endurance/

Operating

Device

Device: SST26VF064B = 64 Mbit, 2. 7-3.6V, SQI Flash Memory

WP#/Hold# pin Enable at power-up

SST26VF064BA = 64 Mbit, 2.7-3.6V, SQI Flash Memory

WP#/Hold# pin Disable at power-up

Tape and

Reel Flag: T = Tape and Reel

Operating

Frequency: 104 = 104 MHz

Endurance: 5 = 100,000 cycles

Temperature: I = -40°C to +85°C

Package: MF = WSON (6mm x 5mm Body), 8-lead

SM = SOIC (200 mil Body), 8-lead

SO = SOIC (300 mil Body), 16-lead

TD = TBGA(>1mm pitch, <1.2mmheight),

24-lead

Valid Combinations:

SST26VF064B-104-5I-MF

SST26VF064BT-104-5I-MF

SST26VF064BA-104-5I-MF

SST26VF064BAT-104-5I-MF

SST26VF064B-104-5I-SM

SST26VF064BT-104-5I-SM

SST26VF064BA-104-5I-SM

SST26VF064BAT-104-5I-SM

SST26VF064B-104-5I-SO

SST26VF064BT-104-5I-SO

SST26VF064BA-104-5I-SO

SST26VF064BAT-104-5I-SO

SST26VF064B-104-5I-TD

SST26VF064BT-104-5I-TD

SST26VF064BA-104-5I-TD

SST26VF064BAT-104-5I-TD

Tape/Reel

Indicator Frequency

Package

Temperature

 2013 Microchip Technology Inc. Advance Information DS25119C-page 51

SST26VF064B / SST26VF064BA

10.0 PACKAGING DIAGRAMS

SST26VF064B / SST26VF064BA

DS25119C-page 52 Advance Information  2013 Microchip Technology Inc.

 2013 Microchip Technology Inc. Advance Information DS25119C-page 53

SST26VF064B / SST26VF064BA

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

SST26VF064B / SST26VF064BA

DS25119C-page 54 Advance Information  2013 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2013 Microchip Technology Inc. Advance Information DS25119C-page 55

SST26VF064B / SST26VF064BA

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

SST26VF064B / SST26VF064BA

DS25119C-page 56 Advance Information  2013 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2013 Microchip Technology Inc. Advance Information DS25119C-page 57

SST26VF064B / SST26VF064BA

DS25119C-page 58 Advance Information  2013 Microchip Technology Inc.

 2013 Microchip Technology Inc. Advance Information DS25119C-page 59

SST26VF064B / SST26VF064BA

11.0 APPENDIX

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (1 OF 11)

Address Bi t Add r e s s Data Comments

SFDP Header

SFDP Header: 1st DWORD

00H A7:A0 53H SFDP Signature

SFDP Signature=50444653H

01H A15:A846H

02H A23:A16 44H

03H A31:A24 50H

SFDP Header: 2nd DWORD

04H A7:A0 00H SFDP Minor Revision Number

05H A15:A801H SFDP Major Revision Number

06H A23:A16 02H Number of Parameter Headers (NPH)

07H A31:A24 FFH Unused. Contains FF and can not be changed.

P a rameter Headers

JEDEC Flash Parameter Header: 1st DWORD

08H A7:A0 00H

ID Number.

When this field is set to 00H, it indicates a JEDEC-specifie d header. For

vendor-specified headers, th is field must be set to the vendor’s manufac-

turer ID.

09H A15:A800H

Parameter Table Minor Revision Number

Minor revisions are either clarifications or changes that add parameters

in existing Reserved locations. Minor revisions do NOT change overall

structure of SFDP. Minor Revision starts at 00H.

0AH A23:A16 01H

Parameter Table Major Revision Number

Major revisions are changes that reorganize or add parameters to loca-

tions that are NOT currently Reserved. Major revisions would require

code (BIOS/firmware) or hardware change to get previously defined dis-

coverable parameters. Major Revision starts at 01H

0BH A31:A24 09H Parameter Table Le ngth

Number of DWORDs that are in the Parameter table

JEDEC Flash Parameter Header: 2nd DWORD

0CH A7:A0 30H Parameter Table Pointer (PTP)

A 24-bit address that specifies the start of this header’s Parameter table

in the SFDP structure. The address must be DWORD-aligned.

0DH A15:A800H

0EH A23:A16 00H

0FH A31:A24 FFH Unused. Contains FF and can not be changed.

JEDEC Flash Parameter Header: 3rd DWORD

10H A7:A0 00H

ID Number.

When this field is set to 00H, it indicates a JEDEC-specifie d header. For

vendor-specified headers, th is field must be set to the vendor’s manufac-

turer ID.

11H A15:A8FFH

Parameter Table Minor Revision Number

Minor revisions are either clarifications or changes that add parameters

in existing Reserved locations. Minor revisions do NOT change overall

structure of SFDP. Minor Revision starts at 00H.

SST26VF064B / SST26VF064BA

DS25119C-page 60 Advance Information  2013 Microchip Technology Inc.

12H A23:A16 FFH

Parameter Table Major Revision Number

Major revisions are changes that reorganize or add parameters to loca-

tions that are NOT currently Reserved. Major revisions would require

code (BIOS/firmware) or hardware change to get previously defined dis-

coverable parameters. Major Revision starts at 01H

13H A31:A24 00H Parameter Table Length

Number of DWORDs that are in the Parameter table

JEDEC Flash Parameter Header: 4th DWORD

14H A7:A0 FFH Parameter Table Pointer (PTP)

This 24-bit address specifies the start of this header’s Parameter Table in

the SFDP structure. The address must be DWORD-aligned.

15H A15:A8FFH

16H A23:A16 FFH

17H A31:A24 FFH Unused. Contains FF can not be changed.

Microc hip (Vendor) Parameter Header: 5th DWORD

18H A7:A0 BFH ID Number

Manufacture ID (vendor specified header)

19H A15:A800H Parameter Table Minor Revision Number

1AH A23:A16 01H Parameter Table major Revision Number, Revision 1.0

1BH A31:A24 18HParameter Table Length, 24 Double Words

Microc hip (Vendor) Parameter Header: 6th DWORD

1CH A7:A0 00H Parameter Table Pointer (PTP)

This 24-bit address specifies the start of this header’s Parameter Table in

the SFDP structure. The address must be DWORD-aligned.

1DH A15:A802H

1EH A23:A16 00H

1FH A31:A24 FFH Unused. Contains FF can not be changed.

JEDEC Fl as h Parame te r Table

JEDEC Flash Parameter Table: 1st DWORD

30H

A1:A0

FDH

Block/Sector Erase Sizes

00: Reserved

01: 4 KByte Erase

10: Reserved

11: Use this setting only if the 4 Kilobyte erase is unavailable.

Write Granularity

0: Single-byte prog rammable devices or buffer programmable devices

with buffer is less than 64 bytes (32 Words).

1: For buffer programmable devices when the buffer size is 64

bytes (32 Words) or larger.

Write Enable Instruction Required for Writing to Volatile Status Reg-

ister

0: Target flash has nonvolatile status bit. Write/Erase commands do

not require status register to be written on every power on.

1: Target flash requires 0x00 to be written to the status register in

orde r to al low write and Erase

A4 Write Enable Opcode Select for W riting to Volatile S t atus Register

0: 0x50. Enables a status register write when bit 3 is set to 1.

1: 0x06 Enables a status register write when bit 3 is set to 1.

A7:A5 Unused. Contains 111b and can not be changed

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (2 OF 11)

Address Bi t Add r e s s Data Comments

 2013 Microchip Technology Inc. Advance Information DS25119C-page 61

SST26VF064B / SST26VF064BA

31H A15:A820H 4 KByte Erase Opcode

32H

A16

F1H

Supports (1-1-2) Fast Read

0: (1-1-2) Fast Read NOT supported

1: (1-1-2) Fast Read supported

A18:A17

Address Bytes

Number of bytes used in addressing flash array read, write and erase

00: 3-Byte only addressing

01: 3- or 4-Byte addressing (e.g. defaults to 3-Byte mode; enters 4-Byte

mode on command)

10: 4-Byte only addressing

11: Reserved

A19

Supports Double Transfer Rate (DTR) Clocking

Indicates the de vice supports so me type of double transfer rate clocking.

0: DTR NO T supported

1: DTR Clocking supported

A20

Supports (1-2-2) Fast Read

Device supports single input opcode, dual input address, and dual output

data Fast Read.

0: (1-2-2) Fast Read NOT supported.

1: (1-2-2) Fast Read supported.

A21

Supports (1-4-4) Fast Read

Device supports single input opcode, quad input address, and quad out-

put data Fast Read

0: (1-4-4) Fast Read NOT supported.

1: (1-4-4) Fast Read supported.

A22

Supports (1-1-4) Fast Read

Device supports single input opcode & address and quad output data

Fast Read.

0: (1-1-4) Fast Read NOT supported.

1: (1-1-4) Fast Read supported.

A23 Unused. Contains ‘1’ can not be changed.

33H A31:A24 FFH Unused. Contains FF can not be changed

JEDEC Flash Parameter Table: 2nd DWORD

34H A7:A0 FFH Flash Memory Density

SST26VF064B/064BA = 03FFFF FFH

35H A15:A8FFH

36H A23:A16 FFH

37H A31:A24 03H

JEDEC Flash Parameter Table: 3rd DWORD

38H

A4:A0

44H

(1-4-4) Fast Read Number of Wait states (dummy clocks) needed

before valid outpu t

00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input

address phase instruction

A7:A5

Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode

Bits

010b: 2 dummy clocks (8 mode bits) are needed with a single input

opcode, quad input address and quad output data Fast Read Instruction.

39H A15:A8EBH (1-4-4) Fast Read Opcode

Opcode for single input opcode, quad input address, and quad output

data Fast Read.

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (3 OF 11)

Address Bi t Add r e s s Data Comments

SST26VF064B / SST26VF064BA

DS25119C-page 62 Advance Information  2013 Microchip Technology Inc.

3AH

A20:A16

08H

(1-1-4) Fast Read Number of Wait states (dummy clocks) needed

before valid output

01000b: 8 dummy bits are needed with a single input opcode & address

and quad output data Fast Read Instruction

A23:A21 (1-1-4) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address and

quad output data Fast Read Instruction

3BH A31:A24 6BH (1-1-4) Fast Read Opcode

Opcode for single input opcode & address and quad output data Fast

Read.

JEDEC Flash Parameter Table: 4th DWORD

3CH

A4:A0

08H

(1-1-2) Fast Read Number of Wait states (dummy clocks) needed

before valid output

01000b: 8 dummy clocks are needed with a single input opcode, address

and dual output data fast read instruction.

A7:A5 (1-1-2) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address and

quad output data Fast Read Instruction

3DH A15:A83BH (1-1-2) Fast Read Opcode

Opcode for single input opcode& address and dual output data Fast Read.

3EH A20:A16 42H

(1-2-2) Fast Read Number of Wait states (dummy clocks) needed

before valid output

00010b: 2 clocks of dummy cycle.

A23:A21 (1-2-2) Fast Read Number of Mode Bits (in clocks)

010b: 2 clocks of mode bits are needed

3FH A31:A24 BBH (1-2-2) Fast Read Opcode

Opcode for single input opcode, dual input address, and dual output data

Fast Read.

JEDEC Flash Parameter Table: 5th DWORD

40H

FEH

Supports (2-2-2) Fast Read

Device supports dual input opcode& address and dual output data Fast

Read.

0: (2-2-2) Fast Read NOT supported.

1: (2-2-2) Fast Read supported.

A3:A1 Reserved. Bits default to all 1’s.

Supports (4-4-4) Fast Read

Device supports Quad input opcode & address and quad output data

Fast Read.

0: (4-4-4) Fast Read NOT supported.

1: (4-4-4) Fast Read supported.

A7:A5 Reserved. Bits default to all 1’s.

41H A15:A8FFH Reserved. Bits default to all 1’s.

42H A23:A16 FFH Reserved. Bits default to all 1’s.

43H A31:A24 FFH Reserved. Bits default to all 1’s.

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (4 OF 11)

Address Bi t Add r e s s Data Comments

 2013 Microchip Technology Inc. Advance Information DS25119C-page 63

SST26VF064B / SST26VF064BA

JEDEC Flash Parameter Table: 6th DWORD

44H A7:A0 FFH Reserved. Bits default to all 1’s.

45H A15:A8FFH Reserved. Bits default to all 1’s.

46H A20:A16 00H

(2-2-2) Fast Read Number of Wait states (dummy clocks) needed

before valid outpu t

00000b: No dummy bit is needed

A23:A21 (2-2-2) Fast Read Number of Mode Bits

000b: No mode bits are needed

47H A31:A24 FFH (2-2-2) Fast Read Opcode

Opcode for dual input opcode& address and dual output data Fast Read.

(not supported)

JEDEC Flash Parameter Table: 7th DWORD

48HA7:A0FFHReserved. Bits default to all 1’s.

49H A15:A8FFH Reserved. Bits default to all 1’s.

4AH

A20:A16

44H

(4-4-4) Fast Read Number of Wait states (dummy clocks) needed

before valid outpu t

00100b: 4 clocks dummy are needed with a quad input opcode &

address and quad output data Fast Read Instruction

A23:A21 (4-4-4) Fast Read Number of Mode Bits

010b: 2 clocks mode bits are needed with a quad input opcode & address

and quad output data Fast Read Instruction

4BH A31:A24 0BH (4-4-4) Fast Read Opcode

Opcode for quad input opcode/address, quad output data Fast Read

JEDEC Flash Parameter Table: 8th DWORD

4CH A7:A0 0DH Sector Type 1 Size

8 KByte, Sector/block size = 2N bytes

4DH A15:A8D8HSector Type 1 Opcode

Opcode used to erase the number of bytes specifie d by Sector Type 1

Size (bits 7-0).

4EH A23:A16 0FH Sector Type 2 Size

32 KByte, Sector/block size = 2N bytes

4FH A31:A24 D8HSector Type 2 Opcode

Opcode used to erase the number of bytes specifie d by Sector Type 2

Size (bits23-16).

JEDEC Flash Parameter Table: 9th DWORD

50H A7:A0 10H Sector Type 3 Size

64 KByte, Sector/block size = 2N bytes

51H A15:A8D8HSector Type 3 Opcode

Opcode used to erase the number of bytes specifie d by Sector Type 3

Size (bits7-0).

52H A23:A16 00H Sector Type 4 Size

0x00: this sector type does not exist

53H A31:A24 00H

Sector Type 4 Opcode

Opcode used to erase the number of bytes specifie d by Sector Type 4

Size (bits23-16)

0x00: this sector type does not exist

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (5 OF 11)

Address Bi t Add r e s s Data Comments

SST26VF064B / SST26VF064BA

DS25119C-page 64 Advance Information  2013 Microchip Technology Inc.

SST26VF064B/064B A (Vendor) Parameter Table

SST26VF064B/064BA Identification

200H A7:A0 BFH Manufacturer ID

201H A15:A826H Memory Type

202H A23:A16 43H Device ID

SST26VF064B/064BA=43H

203H A31:A24 FFH Reserved. Bits default to all 1’s.

SST26VF064B/064BA Interface

204H

A2:A0

B9H

Interfaces Supported

000: SPI only

001: Power up default is SPI; Quad can be enabled/disabled

010: Reserved

: :

111: Reserved

A3 Supports Enable Quad

0: not supported

1: supported

A6:A4

Supports Hold#/Reset# Function

000: Hold#

001: Reset#

010: HOLD/Reset#

011: Hold# & I/O when in SQI(4-4-4), 1-4-4 or 1-1-4 Read

A7 Supports Software Reset

0: not supported

1: supported

205H

5FH

Supports Quad Reset

0: not supported

1: supported

A10:A9 Reserved. Bits default to all 1’s

A13:A11 Byte-Program or Page-Program (256 Bytes)

011: Byte Program/Page Program in SPI and Quad Page Program once

Quad is enabled

A14 Program-Erase Suspend Supported

0: Not Supported

1: Program/Erase Suspend Supported

A15 Deep Power-Down Mode Supported

0: Not Supported

1: Deep Power-Down Mode Supported

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (6 OF 11)

Address Bi t Add r e s s Data Comments

 2013 Microchip Technology Inc. Advance Information DS25119C-page 65

SST26VF064B / SST26VF064BA

206H

A16

FDH

OTP Capable (Security ID) Supported

0: not supported

1: supported

A17 Supports Block Group Protect

0: not supported

1: supported

A18Supports Independent Block Protect

0: not supported

1: supported

A19

Supports Independent non Volatile Lock (Block or Sector becomes

OTP)

0: not supported

1: supported

A23:A20 Reserved. Bits default to all 1’s.

207H A31:A24 FFH Reserved. Bits default to all 1’s.

208H A7:A0 70H VDD Minimum Supply Voltage

2.7V (F270H)

209H A15:A8F2H

20AH A23:A16 60H VDD Maximum Supply Volt age

3.6V (F360H)

20BH A31:A24 F3H

20CH A7:A0 32H Typical time out for Byte-Program: 50 µs

Typical time out for Byte Program is in µs. Represented by conversion of

the actual time from the decimal to hexadecimal number.

20DH A15:A8FFH Reserved. Bits default to all 1’s.

20EH A23:A16 0AH Typ time out for page program: 1.0ms (xxH*(0.1ms)

20FH A31:A24 12H Typical time out for Sector-Erase/Block-Erase: 18 ms

T ypical time out for Sector/Block-Erase is in ms. Represented by conversion

of the actual time from the decimal to hexadeci mal num ber.

210H A7:A0 23H Typical time out for Chip-Erase: 35 ms

Typical time out for Chip-Erase is in ms. Represented by conversion of

the actual time from the decimal to hexadecimal number.

211H A15:A846H Max. time out for Byte-Program: 70 µs

Typical time out for Byte Program is in µs. Represented by conversion of

the actual time from the decimal to hexadecimal number.

212H A23:A16 FFH Reserved. Bits default to all 1’s.

213H A31:A24 0FH Max time out for Page-Program: 1.5ms.

Typical time out for Page Program in xxH * (0.1ms) ms

214H A7:A0 19H Max. time out for Sector Erase/Block Erase: 25ms.

Max time out for Sector/Block Erase in ms

215H A15:A832H Max. time out for Chip Erase: 50ms.

Max time out for Chip Erase in ms.

216H A23:A16 0FH Max. time out for Program Security ID: 1.5 ms

Max time out for Program Security ID in xxH*(0.1ms) ms

217H A31:A24 19H Max. time out for Write-Protection Enable Latency: 25 ms

Max time out for Wr ite-Protection Enable Latency is in ms. Represented by con-

version of the actual time from the decimal to hexadecimal number .

218H A23:A16 19H Max. time Write-Suspend Latency: 25 µs

Max time out for Wr ite-Suspend Latency is in µs. Represented by conversion of

the actual time from the dec imal to hexadecimal number .

219H A31:A24 FFH Max. time to Deep Power-Down

0FFH = Reserved

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (7 OF 11)

Address Bi t Add r e s s Data Comments

SST26VF064B / SST26VF064BA

DS25119C-page 66 Advance Information  2013 Microchip Technology Inc.

21AH A23:A16 FFH Max. time out from Deep Power-Down mode to Standby mode

0FFH = Reserved

21BH A31:A24 FFH Reserved. Bits default to all 1’s.

21CH A23:A16 FFH Reserved. Bits default to all 1’s.

21DH A31:A24 FFH Reserved. Bits default to all 1’s.

21EH A23:A16 FFH Reserved. Bits default to all 1’s.

21FH A31:A24 FFH Reserved. Bits default to all 1’s.

Supported Instructions

220H A7:A0 00H No Operatio n

221H A15:A866H Reset Enable

222H A23:A16 99H Reset Memory

223H A31:A24 38HEnable Quad I/O

224H A7:A0 FFH Reset Quad I/O

225H A15:A805H Read Status Register

226H A23:A16 01H Writ e St atus Register

227H A31:A24 35H Read Configuration Register

228H A7:A0 06H Write Enable

229H A15:A804H Write Disable

22AH A23:A16 02H Byte Program or Page Program

22BH A31:A24 32H SPI Quad Page Program

22CH A7:A0 B0H Suspends Program/Erase

22DH A15:A830H Resumes Program/Erase

22EH A23:A16 72H Read Block-Protection register

22FH A31:A24 42H Write Block Protection Regi ster

230H A7:A0 8DH Lock Down Blo ck Protection Register

231H A15:A8E8Hnon-Volatile Write-Lock Down Register

232H A23:A16 98HGlobal Blo ck Pro t ection Unlock

233H A31:A24 88HRead Security ID

234H A7:A0 A5H Program User Security ID Area

235H A15:A885H Lockout Security ID Programming

236H A23:A16 C0H Set Burst Length

237H A31:A24 9FH JEDEC-ID

238H A7:A0 AFH Quad J-ID

239H A15:A85AH SFDP

23AH A23:A16 FFH Deep Power-Do wn Mode

FFH = Reserved

23BH A31:A24 FFH Release Deep Power-Down Mode

FFH = Reserved

23CH A4:A0 06H

(1-4-4) SPI nB Burst with Wrap Number of W ait states (dummy

clocks) needed before valid output

00110b: 6 clocks of dummy cycle

A7:A5 (1-4-4) SPI nB Burst with Wrap Number of Mode Bits

000b: Set Mode bits are not supported

23DH A15:A8ECH (1-4-4) SPI nB Burst with Wrap Opcode

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (8 OF 11)

Address Bi t Add r e s s Data Comments

 2013 Microchip Technology Inc. Advance Information DS25119C-page 67

SST26VF064B / SST26VF064BA

23EH A20:A16 06H

(4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy

clocks) needed before valid output

00110b: 6 clocks of dummy cycle

A23:A21 (4-4-4) SQI nB Burst with Wrap Numb er of Mod e Bits

000b: Set Mode bits are not supported

23FH A31:A24 0CH (4-4-4) SQI nB Burst with Wrap Opcode

240H A4:A0 00H

(1-1-1) Read Memory Number of W ait states (dummy clocks) needed

before valid outpu t

00000b: Wait states/dummy clocks are not supported.

A7:A5 (1-1-1) Read Memory Number of Mode Bits

000b: Mode bits are not supported,

241H A15:A803H (1-1-1) Read Memory Opcode

242H A20:A16 08H

(1-1-1) Read Memory at Higher Speed Number of Wait states

(dummy clocks) needed before valid output

01000: 8 clocks (8 bits) of dummy cycle

A23:A21 (1-1-1) Read Memory at Higher Speed Number of Mode Bits

000b: Mode bits are not supported,

243H A31:A24 0BH (1-1-1) Read Memory at Higher Spee d Opcode

244H A7:A0 FFH Reserved. Bits default to all 1’s.

245H A15:A8FFH Reserved. Bits default to all 1’s.

246H A23:A16 FFH Reserved. Bits default to all 1’s.

247H A31:A24 FFH Reserved. Bits default to all 1’s.

Security ID

248HA7:A0 FFHSecurity ID size in bytes

Example: If the size is 2 KBytes, this field would be 07FFH

249H A15:A807H

24AH A23:A16 FFH Reserved. Bits default to all 1’s.

24BH A31:A24 FFH Reserved. Bits default to all 1’s.

Memory Organization/Block Protection Bit Mapping 1

24CH A7:A0 01H Section 1: Sector Type Number:

Sector type in JEDEC Parameter Table (bottom, 8 KByte)

24DH A15:A802H Section 1 Number of Sectors

Four of 8KB block (2n)

24EH A23:A16 FFH

Section 1 Block Protection Bit Start

((2m) +1)+ c, c=FFH or -1, m= 7 for 64 Mb

Address bits are Read Lock bit locations and Even Address bits are Write

Lock bit locations. The most significant (left-most) bit indicates the sign of

the integer; it is sometimes called the sign bit. If the sign bit is zero, then

the number is greater than or equal to zero, or positive. If the sign bit is

one then the number is less than zero or negative.

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (9 OF 11)

Address Bi t Add r e s s Data Comments

Security ID Range

Unique ID

(Pre-programmed at factory) 0000H - 0007H

User Programmable 0008H - 07FFH

SST26VF064B / SST26VF064BA

DS25119C-page 68 Advance Information  2013 Microchip Technology Inc.

24FH A31:A24 06H

Section 1 (bottom) Block Protection Bit End

((2m) +1)+ c, c=06H or 6, m= 7 for 64 Mb

Address bits are Read Lock bit locations and Even Address bits are Write

Lock bit locations. The most significant (left-most) bit indicates the sign of

the integer; it is sometimes called the sign bit. If the sign bit is zero, then

the number is greater than or equal to zero, or positive. If the sign bit is

one then the number is less than zero or negative.

250H A7:A0 02H Section 2: Sector Type Number

Sector type in JEDEC Parameter Table (32KB Block)

251H A15:A800H Section 2 Number of Sectors

One of 32KB Block (2^n, n=0)

252H A23:A16 FDH

Section 2 Block Protection Bit Start

((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb

The most significant (left-most) bit indicates the sign of the integer; it is

sometimes called the sign bit. If the sign bit is zero, then the number is

greater than or equal to zero, or positive . If the sign bit is one then the

number is less than zero or negative.

253H A31:A24 FDH

Section 2 Block Protection Bit End

((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb

The most significant (left-most) bit indicates the sign of the integer; it is

sometimes called the sign bit. If the sign bit is zero, then the number is

greater than or equal to zero, or positive . If the sign bit is one then the

number is less than zero or negative.

254H A7:A0 03H Section 3: Sector Type Number

Sector type in JEDEC Parameter Table (64KB Block)

255H A15:A807H Section 3 Number of Sectors

126 of 64KB Block (2m-2, m= 7 for 64 Mb)

256H A23:A16 00H Section 3 Block Protection Bit St art

Section 3 Block Protection Bit starts at 00H

257H A31:A24 FCH Section 3 Block Protection Bit End

((2m) +1)+ c, c=FCH or -4, m= 7 for 64 Mb

258H A7:A0 02H Section 4: Sector Type Number

Sector type in JEDEC Parameter Table (32KB Block)

259H A15:A800H Section 4 Number of Sectors

One of 32KB Block (2^n, n=0)

25AH A23:A16 FEH

Section 4 Block Protection Bit Start

((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb

The most significant (left-most) bit indicates the sign of the integer; it is

sometimes called the sign bit. If the sign bit is zero, then the number is

greater than or equal to zero, or positive . If the sign bit is one then the

number is less than zero or negative.

25BH A31:A24 FEH

Section 4 Block Protection Bit End

((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb

The most significant (left-most) bit indicates the sign of the integer; it is

sometimes called the sign bit. If the sign bit is zero, then the number is

greater than or equal to zero, or positive . If the sign bit is one then the

number is less than zero or negative.

25CH A7:A0 01H Section 5 Sector Type Number:

Sector type in JEDEC Parameter Table (top, 8 KByte)

25DH A15:A802H Section 5 Number of Sectors

Four of 8KB block (2^n)

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (10 OF 11)

Address Bi t Add r e s s Data Comments

 2013 Microchip Technology Inc. Advance Information DS25119C-page 69

SST26VF064B / SST26VF064BA

25EH A23:A16 07H

Section 5 Block Protection Bit Start

((2m) +1)+ c, c=07H or 7, m= 7 for 64 Mb

Address bits are Read Lock bit locations and Even Address bits are Write

Lock bit locations. The most significant (left-most) bit indicates the sign of

the integer; it is sometimes called the sign bit. If the sign bit is zero, then

the number is greater than or equal to zero, or positive. If the sign bit is

one then the number is less than zero or negative.

25FH A31:A24 0EH

Section 5 (bottom) Block Protection Bit End

(((2m) +1)+ c, c=0EH or 14, m= 7 for 64 Mb,

Address bits are Read Lock bit locations and Even Address bits are Write

Lock bit locations. The most significant (left-most) bit indicates the sign of

the integer; it is sometimes called the sign bit. If the sign bit is zero, then

the number is greater than or equal to zero, or positive. If the sign bit is

one then the number is less than zero or negative.

1. See “Mapping Guidance Details” for more detailed mapping information

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (11 OF 11)

Address Bi t Add r e s s Data Comments

SST26VF064B / SST26VF064BA

DS25119C-page 70 Advance Information  2013 Microchip Technology Inc.

11.1 Mapping Guidance Details

The SFDP Memory Organization/Block Protection Bit

Mapping defines the memory organization including

uniform sector/block sizes and different contiguous

sectors/blocks sizes. In addition, this bit defines the

number of these uniform and different sectors/blocks

from address 000000H to the full range of Memory and

the associated Block Locking Register bits of each sec-

tor/block.

Each major Section is defined as follows:

A Major Section consists of Sector T ype Number , Num-

ber of Sector of this type, and the Block-Protection Bit

S tart/End locations. This is tied directly to JEDEC Flash

Parameter Table Sector Size T ype (in 7th DWORD and

8th DWORD section). Note that the contiguous 4KByte

Sectors across the full memory range are not included

on this section because they are not defined in the

JEDEC Flash Parameter Table Sector Size Type sec-

tion. Only the sectors/blocks that are dependently tied

with the Block-Protection Register bits are defined. A

major section is a partition of contiguous same-size

sectors/blocks. There will be several Major Sections as

you dissect across memory from 000000h to the full

range. Similar sector/b lock size that re-appea r may b e

defined as a different Major Section.

11.1.1 SECTOR TYPE NUMBER

Sector Type Number is the sector/block size typed

defined in JEDEC Flash Parameter Table: SFDP

address locations 4CH, 4EH, and 50H. For SFDP

address location 4CH, which is Sector Type 1, the size

is represented by 01H; SFDP address location 4EH,

Sector Type 2, size is represented by 02H; SFDP

address location 50H, Sector Type 3, size is repre-

sented by 03H; and SFDP ad dress location 5 2H, Sec-

tor Type 4, size is represented by 04H. Contiguous

Same Sector Type # Size can re-emerge across the

memory range and this Sector Type # will indicate that

it is a separate/independent Major Section from the

previous contiguous sectors/blocks.

11.1.2 NUMBER OF SECTORS

Number of Sectors represents the number of contigu-

ous sectors/blocks with similar size. A formula calcu-

lates the contiguous sectors/blocks with similar size.

Given the sector/block size, type, and the number of

sectors, the address range of these sectors/blocks can

be determined along with specific Block Locking Reg-

ister bits that control the read/write protection of each

sectors/blocks.

11.1.3 BLOCK-PROTECTION REGISTER

BIT START LOCATION (BPSL)

Block-Protection Register Bit Start Location (BPSL)

designates the start bit location in the Block-Protection

tion begins. If the value of BPSL is 00H, this location is

the 0 bit location. If the value is oth er than 0, then this

value is a constant value adder (c) for a given formula,

(2m + 1) + (c). See “Memory Configuration”.

From the initial location, there will be a bit location for

every increment by 1 until it reac hes the Block Protec-

tion Register Bit End Location (BPEL). This number

range from BPSL to BPEL will correspond to, and be

equal to, the number of sectors/blocks on this Major

Section.

11.1.4 BLOCK PROTECTION REGISTER

BIT END LOCATION (BPEL)

Block Protection Register Bit End Location designates

the end bit location in the Block Protection Re gister bit

where the last sector/block of this Major Section ends.

The value in this field is a constant value adder (c) for

a given formula or equation, (2m + 1) + (c). See “Mem-

ory Configuration”

11.1.5 MEMORY CONFIGURATION

For the SST26VF064B/064BA family, the memory con-

figuration is setup with different contiguous block sizes

from bottom to the top of the memory. For example,

starting from bottom of memory it has four 8KByte

blocks, one 32KByte block, x number of 64KByte

blocks depending on memory size, then one 32KByte

block, and four 8KByte block on the top of memory . See

Table 11-3.

TABLE 11-2: SECTION DEFINITION

Major Section X Secti on X: Sector Type Number

Section X: Number of Sectors

Section X: Block-Protection Register Bit Start Location

Section X: Block-Protection Register Bit End Location

 2013 Microchip Technology Inc. Advance Information DS25119C-page 71

SST26VF064B / SST26VF064BA

Classifying these sector/block sizes via the Sector

Type derived from JEDEC Flash Parameter Table:

SFDP address locations 4CH, 4EH, and 50H is as fol-

lows:

• 8KByte Blocks are classified as Sector Type 1

(@4CH of SFDP)

• 32KByte Blocks are classified as Sector Type 2

(@4EH of SFDP)

• 64KByte Blocks are classified as Sector Type 3

(@50H of SFDP)

For the Numb er of Sectors associ ated with the contig-

uous sectors/blocks, a formula is used to determine the

number of sectors/blocks of these Sector Types:

• 8KByte Block (Type 1) is calculated by 2n. n is a

byte.

• 32KByte Block (Type 2) is calculated by 2n. n is a

byte.

• 64KByte Block (Type 3) is calculated by (2m - 2).

m can either be a 4, 5, 6, 7 or 8 depending on the

memory size. This m field is going to be used for

the 64KByte Block Section and will also be used

for the Block Protection Register Bit Location for-

mula.

m will have a constant value for specific densities and

is defined as:

•8Mbit = 4

• 16Mbit = 5

• 32Mbit = 6

• 64Mbit = 7

•128Mbit = 8

Block Protect Register S tart/End Bits are mapped in the

SFDP by using the formula (2m + 1) + (c). “m” is a con-

stant value that represents the different densities from

8Mbit to 128Mbit (used also in the formula calculati ng

number of 64Kbyte Blocks above). The values that are

going to be placed in the Block Protection Bit S t art/End

field table are the constant value adder (c) in the for-

mula and are represented in two’s compliment except

when the value is 00H. If the value is 00H, this location

is the 0 bit location. If the value is other than 0, then this

is a constant value adder (c) that will be used in the for-

mula. The most significant (left most) bit indicates the

sign of the integer; it is sometimes called the sign bit.

If the sign bit is zero, then the number is greater than or

equal to zero, or positive. If the sign bit is one, then the

number is less than zero, or negative.

See Table 11-4 for an example of this formula.

TABLE 11-3: MEMORY BLOCK DIAGRAM REPRESENTATION

8 KByte Bottom Block

(from 000000H) Section 1: Sector Type 1

Section 1: Number of Sectors

Section 1: Block-Protection Register Bit Start Location

Section 1: Block-Protection Register Bit End Location

32 KByte Section 2: Sector Type Numbe r

Section 2: Number of Sectors

Section 2: Block-Protection Register Bit Start Location

Section 2: Block-Protection Register Bit End Location

64 KByte Section 3: Sector Type Numbe r

Section 3: Number of Sectors

Section 3: Block-Protection Register Bit Start Location

Section 3: Block-Protection Register Bit End Location

32 KByte Section 4: Sector Type Numbe r

Section 4: Number of Sectors

Section 4: Block-Protection Register Bit Start Location

Section 4: Block-Protection Register Bit End Location

8 KByte (Top Block) Section 5: Sector Type Number

Section 5: Number of Sectors

Section 5: Block-Protection Register Bit Start Location

Section 5: Block-Protection Register Bit End Location

SST26VF064B / SST26VF064BA

DS25119C-page 72 Advance Information  2013 Microchip Technology Inc.

TABLE 11-4: BPSL/BPEL EQUATION WITH ACTUAL CONSTANT ADDER DERIVED FROM THE

FORMULA (2M + 1) + (C)

Block Size 8 Mbit to 128 Mbit Comments

8 KByte (Type 1) Bottom BPSL = (2m + 1) + 0FFH

BPEL = (2m + 1) + 04H 0FFH = -1; 06H = 6

Odd address bits are Read-Lock bit

locations and even address bits are

Write-Lock bit locations.

32 KByte (Type 2) BPSL = BPEL= (2m + 1) + 0FDH 0FDH= -3

64 KByte (Type 3) BPSL = 00H

BPEL = (2m + 1) + 0FCH 00H is Block-Protection Register bit 0

location; 0FCH = -4

32 KByte (Type 2) BPSL = BPEL= (2m + 1) + 0FEH 0FEH=-2

8 KByte (Type 1) Top BPSL = (2m + 1) + 07H

BPEL = (2m + 1) + 0EH 07H = 7; 0EH = 14

Odd address bits are Read-Lock bit

locations and even address bits are

Write-Lock bit locations.

 2013 Microchip Technology Inc. Advance Information DS25119C-page 73

SST26VF064B / SST26VF064BA

TABLE 11-5: REVISION HISTORY

Revision Description Date

A•Initial release of data sheet Mar 2012

B•Revised figures 5-8-5-10on pages 17-19, figures 5-13-5-15 on pages

21-22, figures 5-25- 5-28 on pages 27- 30, figures 5-36-5-39 on pages

35-35, and figures 5-42-5-43 on pages 37-37

•Updated the SFDP Table: Table 11-1 on page 59

Jun 20 1 2

C•Updated document to new format

•Revised CPNs to reflect the new package codes

•Updated package drawings to the new format

•Revised “Hardware Write Protection” on page 7, “Write-Suspend and

Write-Resume” on page 28, and “Lock-Down Block-Protection Regis-

ter (LBPR)” on page 36

•Updated “Power-Up Specifications” on page 44

Apr 2013

SST26VF064B / SST26VF064BA

DS25119C-page 74 Advance Information  2013 Microchip Technology Inc.

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

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information:

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Users of Microchip products can receive assistance

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Customers should contact their distributor,

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Technical support is available through the web site

at: http://microchip.com/support

 2013 Microchip Technology Inc. Advance Information DS25119C-page 75

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defen d, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip T echnology

Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Technology Germany II GmbH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-62077-134-1

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doin g so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design cent ers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and

analog product s. In addition, Microchip ’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2013 Microchip Technology Inc. Advance Information DS25119C-page 76

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