LP38851T-ADJ/NOPB - NATIONAL SEMICONDUCTOR

LP38851

LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator

with Enable and Soft-Start

Literature Number: SNVS492B

LP38851

September 13, 2011

800 mA Fast-Response High-Accuracy Adjustable LDO

Linear Regulator with Enable and Soft-Start

General Description

The LP38851-ADJ is a high current, fast response regulator

which can maintain output voltage regulation with extremely

low input to output voltage drop. Fabricated on a CMOS pro-

cess, the device operates from two input voltages: VBIAS

provides voltage to drive the gate of the N-MOS power tran-

sistor, while VIN is the input voltage which supplies power to

the load. The use of an external bias rail allows the part to

operate from ultra low VIN voltages. Unlike bipolar regulators,

the CMOS architecture consumes extremely low quiescent

current at any output load current. The use of an N-MOS

power transistor results in wide bandwidth, yet minimum ex-

ternal capacitance is required to maintain loop stability.

The fast transient response of this device makes it suitable

for use in powering DSP, Microcontroller Core voltages and

Switch Mode Power Supply post regulators. The part is avail-

able in PSOP 8–pin, TO-220 7–pin, and TO-263 7-pin pack-

ages.

Dropout Voltage: 115 mV (typical) at 800 mA load current.

Low Ground Pin Current: 10 mA (typical) at 800 mA load

current.

Soft-Start: Programmable Soft-Start time.

Precision ADJ Voltage: ±1.5% for TJ = 25°C, and ±2.0% for

0°C ≤ TJ ≤ +125°C, across all line and load conditions

Features

■Adjustable VOUT range of 0.80V to 1.8V

■Wide VBIAS Supply operating range of 3.0V to 5.5V

■Stable with 10µF Ceramic capacitors

■Dropout voltage of 115 mV (typical) at 800 mA load current

■Precision VADJ across all line and load conditions:

—±1.5% VADJ for TJ = 25°C

—±2.0% VADJ for 0°C ≤ TJ ≤ +125°C

—±3.0% VADJ for -40°C ≤ TJ ≤ +125°C

■Over-Temperature and Over-Current protection

■Available in 8 lead PSOP, 7 lead TO-220 and 7 lead

TO-263 packages

■−40°C to +125°C Operating Junction Temperature Range

Applications

■ASIC Power Supplies in:

- Desktops, Notebooks, and Graphics Cards, Servers

- Gaming Set Top Boxes, Printers and Copiers

■Server Core and I/O Supplies

■DSP and FPGA Power Supplies

■SMPS Post-Regulator

Typical Application Circuit

30002501

LP38851 800 mA Fast-Response High-Accuracy LDO Linear Regulator with Enable and Soft-Start

Ordering Information

VOUT Order Number Package Type Package Drawing Supplied As

ADJ

LP38851S-ADJ TO263-7 TS7B Rail of 45

LP38851SX-ADJ TO263-7 TS7B Tape and Reel of 500

LP38851T-ADJ TO220-7 TA07B Rail of 45

LP38851MR-ADJ PSOP-8 MRA08A Rail of 95

LP38851MRX-ADJ PSOP-8 MRA08A Tape and Reel of 2500

Connection Diagrams

30002502

TO263-7, Top View

30002503

TO220-7, Top View

30002504

PSOP-8, Top View

Pin Descriptions

TO220-7

Pin #

TO263-7

Pin #

PSOP-8

Pin #

Symbol Pin Description

1 1 5 SS Soft-Start capacitor connection. Used to control the rise time of

VOUT at turn-on.

2 2 6 EN Device Enable, High = On, Low = Off.

3 3 7 IN The unregulated voltage input

4 4 4 GND Ground

5 5 1 ADJ The feedback connection to set the output voltage

6 6 2 OUT The regulated output voltage

7 7 3 BIAS The supply for the internal control and reference circuitry.

- - 8 N/C No internal connection

TAB TAB - TAB

The TO220 and TO263 TAB is a thermal and electrical connection

that is physically attached to the backside of the die, and used as

a thermal heat-sink connection. See the Application Information

section for details.

- - DAP DAP

The PSOP DAP is a thermal connection only that is physically

attached to the backside of the die, and used as a thermal heat-

sink connection. See the Application Information section for details.

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LP38851

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C

Lead Temperature

Soldering, 5 seconds 260°C

ESD Rating

Human Body Model (Note 2) ±2 kV

Power Dissipation (Note 3) Internally Limited

VIN Supply Voltage (Survival) −0.3V to +6.0V

VBIAS Supply Voltage (Survival) −0.3V to +6.0V

VSS SoftStart Voltage (Survival) −0.3V to +6.0V

VOUT Voltage (Survival) −0.3V to +6.0V

IOUT Current (Survival) Internally Limited

Junction Temperature −40°C to +150°C

Operating Ratings (Note 1)

VIN Supply Voltage (VOUT + VDO) to VBIAS

VBIAS Supply Voltage

0.8V ≤ VOUT ≤ 1.2V

1.2V < VOUT ≤ 1.8V

3.0V to 5.5V

4.5V to 5.5V

VEN Voltage 0.0V to VBIAS

IOUT 0 mA to 800 mA

Junction Temperature Range

(Note 3)−40°C to +125°C

Electrical Characteristics Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN =

VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface

type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through

test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for

reference purposes only.

Symbol Parameter Conditions Min Typ Max Units

VADJ VADJ Accuracy

VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V,

See (Note 7)

3.0V ≤ VBIAS ≤ 5.5V,

10 mA ≤ IOUT ≤ 800 mA

492.5

485.0 500. 507.5

515.0

VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V,

See (Note 7)

3.0V ≤ VBIAS ≤ 5.5V,

10 mA ≤ IOUT ≤ 800 mA,

0°C ≤ TJ ≤ +125°C

490.0 500. 510.0

VOUT VOUT Range 3.0V ≤ VBIAS ≤ 5.5V 0.80 1.20 V

4.5V ≤ VBIAS ≤ 5.5V 0.80 1.80

ΔVOUT/ΔVIN Line Regulation, VIN (Note 4)VOUT(NOM)+1V ≤ VIN ≤ VBIAS - 0.04 - %/V

ΔVOUT/ΔVBIAS Line Regulation, VBIAS (Note 4)3.0V ≤ VBIAS ≤ 5.5V - 0.10 - %/V

ΔVOUT/ΔIOUT

Output Voltage Load Regulation

(Note 5)10 mA ≤ IOUT ≤ 800 mA - 0.2 - %/A

VDO Dropout Voltage (Note 6)IOUT = 800 mA - 115 150

200 mV

IGND(IN)

Quiescent Current Drawn from

VIN Supply

VOUT = 0.80V

VBIAS = 3.0V

10 mA ≤ IOUT ≤ 800 mA

- 7.0 8.5

9.0 mA

VEN ≤ 0.5V 1 100

300 μA

IGND(BIAS)

Quiescent Current Drawn from

VBIAS Supply

10 mA ≤ IOUT ≤ 800 mA - 3.0 3.8

4.5 mA

VEN ≤ 0.5V 100 170

200 μA

UVLO Under-Voltage Lock-Out

Threshold VBIAS rising until device is functional 2.20

2.00 2.45 2.70

2.90 V

UVLO(HYS)

Under-Voltage Lock-Out

Hysteresis

VBIAS falling from UVLO threshold until

device is non-functional

50 150 300

350 mV

ISC Output Short-Circuit Current VIN = VOUT(NOM) + 1V,

VBIAS = 3.0V, VOUT = 0.0V - 2.3 - A

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LP38851

Symbol Parameter Conditions Min Typ Max Units

Soft-Start

rSS Soft-Start internal resistance 11.0 14.0 17.0 kΩ

tSS

Soft-Start time

tSS = CSS × rSS × 5 CSS = 10 nF - 700 - μs

Enable

IEN ENABLE pin Current

VEN = VBIAS - 0.01 -

μA

VEN = 0.0V, VBIAS = 5.5V -24

-21 -35 -43

-50

VEN(ON) Enable Voltage Threshold VEN rising until Output = ON 1.00

0.90 1.25 1.50

1.55 V

VEN(HYS) Enable Voltage Hysteresis VEN falling from VEN(ON) until Output =

OFF

30 100 150

200 mV

tOFF Turn-OFF Delay Time RLOAD x COUT << tOFF - 20 - µs

tON Turn-ON Delay Time RLOAD x COUT << tON - 15 -

AC Parameters

PSRR

(VIN)

Ripple Rejection for VIN Input

Voltage

VIN = VOUT(NOM) + 1V,

f = 120 Hz - 72 -

VIN = VOUT(NOM) + 1V,

f = 1 kHz - 61 -

PSRR

(VBIAS)Ripple Rejection for VBIAS Voltage

VBIAS = VOUT(NOM) + 3V,

f = 120 Hz - 54 -

VBIAS = VOUT(NOM) + 3V,

f = 1 kHz - 53 -

Output Noise Density f = 120 Hz - 1 - µV/√Hz

Output Noise Voltage BW = 10 Hz − 100 kHz - 150 - µVRMS

BW = 300 Hz − 300 kHz - 90 -

Thermal Parameters

TSD

Thermal Shutdown Junction

Temperature - 160 - °C

TSD(HYS) Thermal Shutdown Hysteresis - 10 -

θJ-A

Thermal Resistance, Junction to

Ambient(Note 3)

TO220-7 - 60 -

°C/W

TO263-7 - 60 -

PSOP-8 - 168 -

θJ-C

Thermal Resistance, Junction to

Case(Note 3, Note 8)

TO220-7 - 3 -

TO263-7 - 3 -

PSOP-8 - 11 -

Note 1: Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the

device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical

Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114.

Note 3: Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal

resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See

the Application Information section for details.

Note 4: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 5: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.

Note 6: Dropout voltage is defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to

drop 2% from the nominal value.

Note 7: VIN cannot exceed either VBIAS or 4.5V, whichever value is lower.

Note 8: For TO-220 and TO-263: θJ-C refers to the BOTTOM surface of the package, under the epoxy body, as the 'CASE'. For PSOP-8: θJ-C refers to the DAP

(aka: Exposed Pad) on BOTTOM surface of the package as the 'CASE'.

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LP38851

Typical Performance Characteristics Refer to the Typical Application Circuit. Unless otherwise

specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF

Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open.

VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS

30002587

VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature

30002561

VIN Ground Pin Current vs Temperature

30002562

Load Regulation vs Temperature

30002563

Dropout Voltage (VDO) vs Temperature

30002565

Output Current Limit (ISC) vs Temperature

30002566

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LP38851

VOUT vs Temperature

30002567

VOUT vs VIN

30002572

UVLO Thresholds vs Temperature

30002568

Soft-Start rSS Variation vs Temperature

30002575

VOUT vs CSS, 10 nF to 47 nF

30002576

Enable Thresholds (VEN) vs Temperature

30002588

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LP38851

Enable Pull-Down Current (IEN) vs Temperature

30002589

Enable Pull-Up Resistor (rEN) vs Temperature

30002590

VIN Line Transient Response

30002577

VIN Line Transient Response

30002578

VBIAS Line Transient Response

30002579

VBIAS Line Transient Response

30002580

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LP38851

Load Transient Response, COUT = 10 µF Ceramic

30002581

Load Transient Response, COUT = 10 µF Ceramic

30002582

Load Transient Response, COUT = 47 µF Ceramic

30002583

Load Transient Response, COUT = 47 µF Ceramic

30002584

Load Transient Response, COUT = 68 µF Tantalum

30002585

Load Transient Response, COUT = 68 µF Tantalum

30002586

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LP38851

VBIAS PSRR

30002570

VIN PSRR

30002571

Output Noise

30002569

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LP38851

Block Diagram

30002505

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LP38851

Application Information

EXTERNAL CAPACITORS

To assure regulator stability, input and output capacitors are

required as shown in the Typical Application Circuit.

Output Capacitor

A minimum output capacitance of 10 µF, ceramic, is required

for stability. The amount of output capacitance can be in-

creased without limit. The output capacitor must be located

less than 1 cm from the output pin of the IC and returned to

the device ground pin with a clean analog ground.

Only high quality ceramic types such as X5R or X7R should

be used, as the Z5U and Y5F types do not provide sufficient

capacitance over temperature.

Tantalum capacitors will also provide stable operation across

the entire operating temperature range. However, the effects

of ESR may provide variations in the output voltage during

fast load transients. Using the minimum recommended 10 µF

ceramic capacitor at the output will allow unlimited capaci-

tance, Tantalum and/or Aluminum, to be added in parallel.

Input Capacitor

The input capacitor must be at least 10 µF, but can be in-

creased without limit. It's purpose is to provide a low source

impedance for the regulator input. A ceramic capacitor, X5R

or X7R, is recommended.

Tantalum capacitors may also be used at the input pin. There

is no specific ESR limitation on the input capacitor (the lower,

the better).

Aluminum electrolytic capacitors can be used, but are not

recommended as their ESR increases very quickly at cold

temperatures. They are not recommended for any application

where the ambient temperature falls below 0°C.

Bias Capacitor

The capacitor on the bias pin must be at least 1 µF, and can

be any good quality capacitor (ceramic is recommended).

Feed Forward Capacitor, CFF

(Refer to the Typical Application Circuit)

When using a ceramic capacitor for COUT, the typical ESR

value will be too small to provide any meaningful positive

phase compensation, FZ, to offset the internal negative phase

shifts in the gain loop.

FZ = 1 / (2 x π x COUT x ESR) (1)

A capacitor placed across the gain resistor R1 will provide

additional phase margin to improve load transient response

of the device. This capacitor, CFF, in parallel with R1, will form

a zero in the loop response given by the formula:

FZ = 1 / (2 x π x CFF x R1) (2)

For optimum load transient response select CFF so the zero

frequency, FZ, falls between 500 kHz and 750 kHz.

CFF = 1 / (2 x π x R1 x FZ) (3)

The phase lead provided by CFF diminishes as the DC gain

approaches unity, or VOUT approaches VADJ. This is because

CFF also forms a pole with a frequency of:

FP = 1 / (2 x π x CFF x (R1 || R2) ) (4)

It's important to note that at higher output voltages, where R1

is much larger than R2, the pole and zero are far apart in fre-

quency. At lower output voltages the frequency of the pole

and the zero mover closer together. The phase lead provided

from CFF diminishes quickly as the output voltage is reduced,

and has no effect when VOUT = VADJ. For this reason, relying

on this compensation technique alone is adequate only for

higher output voltages. For the LP38851, the practical mini-

mum VOUT is 0.8V when a ceramic capacitor is used for

COUT.

30002521

FIGURE 1. FZERO and FPOLE vs Gain

SETTING THE OUTPUT VOLTAGE

(Refer to the Typical Application Circuit)

The output voltage is set using the external resistive divider

R1 and R2. The output voltage is given by the formula:

(5)

The resistors used for R1 and R2 should be high quality, tight

tolerance, and with matching temperature coefficients. It is

important to remember that, although the value of VADJ is

guaranteed, the use of low quality resistors for R1 and R2 can

easily produce a VOUT value that is unacceptable.

It is recommended that the values selected for R1 and R2 are

such that the parallel value is less than 10 kΩ. This is to pre-

vent internal parasitic capacitances on the ADJ pin from

interfering with the FZ pole set by R1 and CFF.

( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ(6)

Table 1 lists some suggested, best fit, standard ±1% resistor

values for R1 and R2, and a standard ±10% capacitor values

for CFF, for a range of VOUT values. Other values of R1, R2,

and CFF are available that will give similar results.

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LP38851

TABLE 1.

VOUT R1 R2 CFF FZ

0.8V 1.07 kΩ1.78 kΩ220 pF 676 kHz

0.9V 1.50 kΩ1.87 kΩ180 pF 589 kHz

1.00V 1.00 kΩ1.00 kΩ270 pF 589 kHz

1.1V 1.65 kΩ1.37 kΩ150 pF 643 kHz

1.2V 1.40 kΩ1.00 kΩ180 pF 631 kHz

1.3V 1.15 kΩ715 Ω 220 pF 629 kHz

1.4V 1.07 kΩ590 Ω 220 pF 676 kHz

1.5V 2.00 kΩ1.00 kΩ120pF 663 kHz

1.6V 1.65 kΩ750 Ω 150 pF 643 kHz

1.7V 2.55 kΩ1.07 kΩ100 pF 624 kHz

1.8V 2.94 kΩ1.13 kΩ82 pF 660 kHz

Please refer to Application Note AN-1378 for additional infor-

mation on how resistor tolerances affect the calculated VOUT

value.

INPUT VOLTAGE

The input voltage (VIN) is the high current external voltage rail

that will be regulated down to a lower voltage, which is applied

to the load. The input voltage must be at least VOUT + VDO,

and no higher than whatever value is used for VBIAS.

For applications where VBIAS is higher than 4.5V, VIN must be

no greater than 4.5V, otherwise output voltage accuracy may

be affected.

BIAS VOLTAGE

The bias voltage (VBIAS) is a low current external voltage rail

required to bias the control circuitry and provide gate drive for

the N-FET pass transistor. When VOUT is set to 1.20V, or less,

VBIAS may be anywhere in the operating range of 3.0V to 5.5V.

If VOUT is set higher than 1.20V , VBIAS must be between 4.5V

and 5.5V to ensure proper operation of the device.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the

device from functioning when the bias voltage is below the

Under-Voltage Lock-Out (UVLO) threshold of approximately

2.45V.

As the bias voltage rises above the UVLO threshold the de-

vice control circuitry becomes active. There is approximately

150 mV of hysteresis built into the UVLO threshold to provide

noise immunity.

When the bias voltage is between the UVLO threshold and

the Minimum Operating Rating value of 3.0V the device will

be functional, but the operating parameters will not be within

the guaranteed limits.

SUPPLY SEQUENCING

There is no requirement for the order that VIN or VBIAS are

applied or removed.

One practical limitation is that the Soft-Start circuit starts

charging CSS when both VBIAS rises above the UVLO thresh-

old and the Enable pin is above the VEN(ON) threshold. If the

application of VIN is delayed beyond this point the benefits of

Soft-Start will be compromised.

In any case, the output voltage cannot be guaranteed until

both VIN and VBIAS are within the range of guaranteed oper-

ating values.

If used in a dual-supply system where the regulator output

load is returned to a negative supply, the output pin must be

diode clamped to ground. A Schottky diode is recommended

for this diode clamp.

REVERSE VOLTAGE

A reverse voltage condition will exist when the voltage at the

output pin is higher than the voltage at the input pin. Typically

this will happen when VIN is abruptly taken low and COUT con-

tinues to hold a sufficient charge such that the input to output

voltage becomes reversed.

The NMOS pass element, by design, contains no body diode.

This means that, as long as the gate of the pass element is

not driven, there will not be any reverse current flow through

the pass element during a reverse voltage event. The gate of

the pass element is not driven when VBIAS is below the UVLO

threshold, or when the Enable pin is held low.

When VBIAS is above the UVLO threshold, and the Enable pin

is above the VEN(ON) threshold, the control circuitry is active

and will attempt to regulate the output voltage. Since the input

voltage is less than the output voltage the control circuit will

drive the gate of the pass element to the full VBIAS potential

when the output voltage begins to fall. In this condition, re-

verse current will flow from the output pin to the input pin ,

limited only by the RDS(ON) of the pass element and the output

to input voltage differential. Discharging an output capacitor

up 1000 µF in this manner will not damage the device as the

current will rapidly decay. However, continuous reverse cur-

rent should be avoided.

SOFT-START

The LP38851 incorporates a Soft-Start function that reduces

the start-up current surge into the output capacitor (COUT) by

allowing VOUT to rise slowly to the final value. This is accom-

plished by controlling VREF at the SS pin. The soft-start timing

capacitor (CSS) is internally held to ground until both VBIAS

rises above the Under-Voltage Lock-Out threshold (ULVO)

and the Enable pin is higher than the VEN(ON) threshold.

VREF will rise at an RC rate defined by the internal resistance

of the SS pin (rSS), and the external capacitor connected to

the SS pin. This allows the output voltage to rise in a con-

trolled manner until steady-state regulation is achieved. Typ-

ically, five time constants are recommended to assure that the

output voltage is sufficiently close to the final steady-state

value. During the soft-start time the output current can rise to

the built-in current limit.

Soft-Start Time = CSS × rSS × 5 (7)

Since the VOUT rise will be exponential, not linear, the in-rush

current will peak during the first time constant (τ), and VOUT

will require four additional time constants (4τ) to reach the final

value (5τ) .

After achieving normal operation, should either VBIAS fall be-

low the ULVO threshold, or the Enable pin fall below the VEN

(OFF) threshold, the device output will be disabled and the Soft-

Start capacitor (CSS) discharge circuit will become active. The

CSS discharge circuit will remain active until VBIAS falls to 500

mV (typical). When VBIAS falls below 500 mV (typical), the

CSS discharge circuit will cease to function due to a lack of

sufficient biasing to the control circuitry.

Since VREF appears on the SS pin, any leakage through CSS

will cause VREF to fall, and thus affect VOUT. A leakage of 50

nA (about 10 MΩ) through CSS will cause VOUT to be approx-

imately 0.1% lower than nominal, while a leakage of 500 nA

(about 1 MΩ) will cause VOUT to be approximately 1% lower

than nominal. Typical ceramic capacitors will have a factor of

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LP38851

10X difference in leakage between 25°C and 85°C, so the

maximum ambient temperature must be included in the ca-

pacitor selection process.

Typical CSS values will be in the range of 1 nF to 100 nF,

providing typical Soft-Start times in the range of 70 μs to 7 ms

(5τ). Values less than 1 nF can be used, but the Soft-Start

effect will be minimal. Values larger than 100 nF will provide

soft-start, but may not be fully discharged if VBIAS falls from

the UVLVO threshold to less than 500 mV in less than 100

µs.

Figure 2 shows the relationship between the COUT value and

a typical CSS value.

30002523

FIGURE 2. Typical CSS vs COUT Values

The CSS capacitor must be connected to a clean ground path

back to the device ground pin. No components, other than

CSS, should be connected to the SS pin, as there could be

adverse effects to VOUT.

If the Soft-Start function is not needed the SS pin should be

left open, although some minimal capacitance value is always

recommended.

ENABLE OPERATION

The Enable pin (EN) provides a mechanism to enable, or dis-

able, the regulator output stage. The Enable pin has an

internal pull-up, through a typical 160 kΩ resistor, to VBIAS.

If the Enable pin is actively driven, pulling the Enable pin

above the VEN threshold of 1.25V (typical) will turn the regu-

lator output on, while pulling the Enable pin below the VEN

threshold will turn the regulator output off. There is approxi-

mately 100 mV of hysteresis built into the Enable threshold

provide noise immunity.

If the Enable function is not needed this pin should be left

open, or connected directly to VBIAS. If the Enable pin is left

open, stray capacitance on this pin must be minimized, oth-

erwise the output turn-on will be delayed while the stray

capacitance is charged through the internal resistance (rEN).

POWER DISSIPATION AND HEAT-SINKING

Additional copper area for heat-sinking may be required de-

pending on the maximum device dissipation (PD) and the

maximum anticipated ambient temperature (TA) for the de-

vice. Under all possible conditions, the junction temperature

must be within the range specified under operating condi-

tions.

The total power dissipation of the device is the sum of three

different points of dissipation in the device.

The first part is the power that is dissipated in the NMOS pass

element, and can be determined with the formula:

PD(PASS) = (VIN - VOUT) × IOUT (8)

The second part is the power that is dissipated in the bias and

control circuitry, and can be determined with the formula:

PD(BIAS) = VBIAS × IGND(BIAS) (9)

where IGND(BIAS) is the portion of the operating ground current

of the device that is related to VBIAS.

The third part is the power that is dissipated in portions of the

output stage circuitry, and can be determined with the formu-

la:

PD(IN) = VIN × IGND(IN) (10)

where IGND(IN) is the portion of the operating ground current

of the device that is related to VIN.

The total power dissipation is then:

PD = PD(PASS) + PD(BIAS) + PD(IN) (11)

The maximum allowable junction temperature rise (ΔTJ) de-

pends on the maximum anticipated ambient temperature

(TA) for the application, and the maximum allowable operating

junction temperature (TJ(MAX)) .

(12)

The maximum allowable value for junction to ambient Ther-

mal Resistance, θJA, can be calculated using the formula:

(13)

Heat-Sinking The TO-220 Package

The TO220-5 package has a θJA rating of 60°C/W and a θJC

rating of 3°C/W. These ratings are for the package only, no

additional heat-sinking, and with no airflow. If the needed

θJA, as calculated above, is greater than or equal to 60°C/W

then no additional heat-sinking is required since the package

can safely dissipate the heat and not exceed the operating

TJ(MAX). If the needed θJA is less than 60°C/W then additional

heat-sinking is needed.

The thermal resistance of a TO-220 package can be reduced

by attaching it to a heat sink or a copper plane on a PC board.

If a copper plane is to be used, the values of θJA will be same

as shown in next section for TO-263 package.

The heat-sink to be used in the application should have a

heat-sink to ambient thermal resistance, θHA:

(14)

where θJA is the required total thermal resistance from the

junction to the ambient air, θCH is the thermal resistance from

the case to the surface of the heart-sink, and θJC is the thermal

resistance from the junction to the surface of the case.

13 www.national.com

LP38851

For this equation, θJC is about 3°C/W for a TO-220 package.

The value for θCH depends on method of attachment, insula-

tor, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the

heat-sink manufacturer datasheet for details and recommen-

dations.

Heat-Sinking The TO-263 Package

The TO-263 package has a θJA rating of 60°C/W, and a θJC

rating of 3°C/W. These ratings are for the package only, no

additional heat-sinking, and with no airflow.

The TO-263 package uses the copper plane on the PCB as

a heat-sink. The tab of this package is soldered to the copper

plane for heat sinking. Figure 3 shows a curve for the θJA of

TO-263 package for different copper area sizes, using a typ-

ical PCB with 1 ounce copper and no solder mask over the

copper area for heat-sinking.

30002525

FIGURE 3. θJA vs Copper (1 Ounce) Area for the TO-263

package

Figure 3 shows that increasing the copper area beyond 1

square inch produces very little improvement. The minimum

value for θJA for the TO-263 package mounted to a PCB is

32°C/W.

30002526

FIGURE 4. Maximum Power Dissipation vs Ambient

Temperature for the TO-263 Package

Figure 4 shows the maximum allowable power dissipation for

TO-263 packages for different ambient temperatures, assum-

ing θJA is 35°C/W and the maximum junction temperature is

125°C.

Heat-Sinking The PSOP-8 Package

The LP38851MR package has a θJA rating of 168°C/W, and

a θJC rating of 11°C/W. The θJA rating of 168°C/W includes

the device DAP soldered to an area of 0.008 square inches

(0.09 in x 0.09 in) of 1 ounce copper, with no airflow.

30002527

FIGURE 5. θJA vs Copper (1 Ounce) Area for the PSOP-8

Package

Increasing the copper area soldered to the DAP to 1 square

inch of 1 ounce copper, using a dog-bone type layout, will

improve the θJA rating to 98°C/W. Figure 5 shows that in-

creasing the copper area beyond 1 square inch produces very

little improvement.

30002528

FIGURE 6. Maximum Power Dissipation vs Ambient

Temperature for the PSOP-8 Package

Figure 6 shows the maximum allowable power dissipation for

the PSOP-8 package for a range of ambient temperatures,

assuming θJA is 98°C/W and the maximum junction temper-

ature is 125°C.

www.national.com 14

LP38851

Physical Dimensions inches (millimeters) unless otherwise noted

TO-220 7-Lead, Stagger Bend Package (TO220-7)

NS Package Number TA07B

TO-263 7-Lead, Molded, Surface Mount Package (TO263-7)

NS Package Number TS7B

15 www.national.com

LP38851

PSOP, 8 Lead, Molded, 0.050 in Pitch

NS Package Number MRA08A

www.national.com 16

LP38851

Notes

17 www.national.com

LP38851

Notes

LP38851 800 mA Fast-Response High-Accuracy LDO Linear Regulator with Enable and Soft-Start

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